Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.

Abstract: A method for manufacturing a semiconductor feature includes: alternatingly forming first and second dielectric layers on a semiconductor substrate along a vertical direction; forming multiple spaced-apart trenches penetrating the first and second dielectric layers; forming multiple support segments filling the trenches; removing the second dielectric layers to form multiple spaces; forming multiple conductive layers filling the spaces; removing the support segments to expose the conductive layers and the first dielectric layers; selectively forming a blocking layer covering the first dielectric layers outside of the conductive layers; forming multiple selectively-deposited sub-layers on the exposed conductive layers outside of the blocking layer and each connected to one of the conductive layers; forming multiple channel sub-layers on the selectively-deposited sub-layers outside of the blocking layer; removing the blocking layer; forming multiple isolation sub-layers filling the trenches; and forming multiple

Abstract: Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ?3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ?7 nm).

Abstract: A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.

Abstract: Disclosed a capacitive stylus pen, comprising a holding structure comprising a pen holder, and a pen tip assembly comprising a pen tip shaft and a strain sensor, the strain sensor comprising a resilient element and a strain gauge on the resilient element, and the resilient element being connected to the pen tip shaft and the holding structure, wherein the resilient element is L-shaped, the pen tip assembly further comprises an energy absorption structure arranged on the pen tip shaft, and the energy absorption structure is connected to the holding structure. The L-shaped resilient element in cooperation with the energy absorption structure forms a double-support elastic buffering structure and reduces deformation rate of the strain gauge with same load when the capacitive stylus pen itself rotates to different angles; and the energy absorption structure is added to share part of the stress on the resilient element to reduce the resilient element's deformation.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first conductive structure arranged over a substrate. A memory layer is arranged over the first conductive structure, below a second conductive structure, and includes a ferroelectric material. An annealed seed layer is arranged between the first and second conductive structures and directly on a first side of the memory layer. An amount of the crystal structure that includes an orthorhombic phase is greater than about 35 percent.

Abstract: A computing device is described that determines, by executing a first application, a thematic texture of a second application separate from the first application. Additionally, the computing device determines, by executing the first application and based at least in part on the thematic texture of the second application, a texture. The computing device assigns, by executing the first application, the determined texture to a region of a graphical keyboard.

Abstract: A mobile computing device is described that outputs, for display at a presence-sensitive display component, a graphical user interface that includes an edit region and a graphical keyboard including a plurality of keys and a translation region. The device determines one or more keys from the plurality of keys selected by an input, determines, based on the one or more keys, one or more candidate words from a source language, and outputs, for display, within the edit region, an indication of at least one candidate word from the one or more candidate words. The device determines a translation of a particular word from the at least one candidate word that is associated with a destination language that is different than the source language, and outputs, for display within the translation region, an indication of the translation of the particular word.

Abstract: A computing device is described that determines, by executing a first application, a thematic texture of a second application separate from the first application. Additionally, the computing device determines, by executing the first application and based at least in part on the thematic texture of the second application, a texture. The computing device assigns, by executing the first application, the determined texture to a region of a graphical keyboard.

Abstract: In one example, a computing device includes at least one processor configured to output for display, a graphical keyboard. The at least one processor may also be configured to model, in a first lattice, a plurality of candidate character strings that include symbols of a first alphabet. The first lattice may indicate spatial probabilities of the plurality of candidate character strings. The at least one processor may be configured to determine, using a second lattice that indicates probabilities of one or more words of a second language based at least in part on the spatial probabilities of the plurality of candidate character strings, a probability that the at least one of the plurality of candidate character strings corresponds to at least one word included in the second language. The at least one processor may be configured to output for display, the one or more symbols representing at least one word.

Abstract: Methods, systems, and computer program products for generating a search of attachments are described. A search request based on a business template is obtained, the business template comprising a node containing an identity of an entity to which the attachment is attached and an attachment sub-node. A search request based on an attachment template is obtained, the attachment template comprising a root node referring to the attachment sub-node of the business template and a node containing an identity of the attachment. A search is performed based on the business template and the attachment template.