Patents by Inventor SONG HE
SONG HE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030168184Abstract: A friction transmission mechanism for a motor-driven blind is constructed to include a driving unit, and at least one cord roll-up unit controlled to the driving unit to lift/lower or tilt the slats of the motor-driven Venetian blind. Each cord roll-up unit includes an amplitude modulation wheel controlled by the driving unit to lift/lower the slats and bottom rail of the Venetian blind, a frequency modulation wheel for rotation with the amplitude modulation set to tilt the slats of the Venetian blind, spring means, which forces the frequency modulation wheel into friction-engagement with the amplitude modulation wheel, and a support supporting the amplitude modulation wheel, the support having a shoulder adapted to act with a protruding block of the frequency modulation wheel and to further limit angle of rotation of the frequency modulation wheel.Type: ApplicationFiled: May 14, 2002Publication date: September 11, 2003Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Che Wen, Song-He Lui
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Publication number: 20030168185Abstract: An electromagnetic clutch-controlled electric blind is constructed to include a blind body formed of a headrail defining a receiving chamber, a set of slats, and a bottom rail, a power drive, the power drive including a reversible motor and electromagnetic clutch means connectable to the motor, an amplitude modulation set coupled to the motor for rotation with the motor to lift/lower the slats to the desired elevation, a frequency modulation set coupled to the motor through the electromagnetic clutch means and adapted for controlling tilting angle of the slats.Type: ApplicationFiled: May 14, 2002Publication date: September 11, 2003Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Che Wen, Song-He Lui, Ya-Wei Hsu
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Publication number: 20030168186Abstract: A plug-in transmission mechanism for a motor-driven blind is constructed to include a driving unit, two cord roll-up units controlled by the driving unit to lift/lower or tilt the slats of the motor-driven Venetian blind. Each cord roll-up unit includes an amplitude modulation wheel rotated by the driving unit to lift/lower the slats and bottom rail of the Venetian blind, a frequency modulation wheel for rotation with the amplitude modulation wheel to tilt the slats of the Venetian blind, a stop block adapted to limit the angle of rotation of the frequency modulation wheel, and a link supported on a spring in a longitudinal groove of the amplitude modulation wheel and detachably engaged into a notch of the frequency modulation wheel to control linkage between the amplitude modulation wheel and the frequency modulation wheel.Type: ApplicationFiled: May 14, 2002Publication date: September 11, 2003Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Che Wen, Song-He Lui
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Publication number: 20030168188Abstract: A screw transmission mechanism for a motor-driven blind is constructed to include a driving unit, and at least one cord roll-up unit controlled by the driving unit to lift/lower or tilt the slats of the motor-driven Venetian blind. Each cord roll-up unit includes an amplitude modulation set controlled by the driving unit to lift/lower the slats and bottom rail of the Venetian blind, a frequency modulation set for rotation with the amplitude modulation set to tilt the slats of the Venetian blind, and a linkage adapted to control connection between the frequency modulation set and the amplitude modulation set.Type: ApplicationFiled: May 30, 2002Publication date: September 11, 2003Applicant: Industrial Technology Research InstituteInventors: Yu-Che Wen, Song-He Lui
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Patent number: 6617639Abstract: A floating gate flash memory device including a substrate comprising a source region, a drain region, and a channel region positioned therebetween; a floating gate electrode positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and a control gate electrode positioned above the floating gate electrode and separated from the floating gate electrode by an interpoly dielectric layer, the interpoly dielectric layer comprising a modified ONO structure having a bottom dielectric material layer adjacent to the floating gate electrode, a top dielectric material layer adjacent to the control gate electrode, and a center layer comprising a nitride and positioned between the bottom dielectric material layer and the top dielectric material layer, in which the tunnel dielectric material layer, and at least one of the bottom dielectric material layer and the top dielectric material layer, comprise a high-K dielectric material.Type: GrantFiled: June 21, 2002Date of Patent: September 9, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Zhigang Wang, Xin Guo, Yue-Song He
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Patent number: 6580639Abstract: The present invention makes use of ion bombardment to amorphize the source and drain regions of a short channel FET prior to implanting. The source/drain implants are then localized to a shallow depth by appropriate choice of implanting conditions, typically employing rather low bombardment voltages of approximately 10 KeV. Amorphous source/drain regions substantially hinder the diffusion of source/drain dopants and thereby reduce the possibility of punchthrough and loss of FET function. Such devices are preferably used in NAND type flash memory devices maintaining proper self-boosting voltages and FET functions even when short channel lengths are employed.Type: GrantFiled: August 10, 1999Date of Patent: June 17, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Yue-Song He, Kent Kuohua Chang, Allen U. Huang
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Patent number: 6570211Abstract: The invention relates to a flash memory devices and a method associated therewith in which combined source/drain regions are shared by more than two memory cells. For example, source/drain regions can be shared by four adjacent memory cells. Such sharing can be accomplished by providing memory cells along main branches of word lines and additional memory cells along dead end branches extending off the main branches. Another aspect of the invention relates to a flash memory device wherein the memory cells are arrayed and a first portion of the memory cells are read with source and drain regions sharing a row of the array and a second portion of the memory cells are read with source and drain regions sharing a column of the array.Type: GrantFiled: June 26, 2002Date of Patent: May 27, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Yue-song He, Richard Fastow, Zheng Wei
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Patent number: 6541338Abstract: A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.Type: GrantFiled: July 30, 2001Date of Patent: April 1, 2003Assignee: Advanced Micro Devices Inc.Inventors: Zhigang Wang, Yue-Song He, Richard Fastow
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Source side boron implanting and diffusing device architecture for deep sub 0.18 micron flash memory
Patent number: 6524914Abstract: One aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.Type: GrantFiled: October 30, 2000Date of Patent: February 25, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Yue-song He, Sameer Haddad, Timothy Thurgate, Chi Chang -
Publication number: 20030022440Abstract: A method of forming flash memory EEPROM devices having a low energy source implant and a high-energy VSS connection implant such that the intrinsic source defect density is reduced and the VSs resistance is low. The source regions are implanted with a low energy, low dosage dopant ions and the VSS regions are implanted with a high energy, high dosage dopant ions.Type: ApplicationFiled: July 30, 2001Publication date: January 30, 2003Inventors: Zhigang Wang, Yue-Song He, Richard Fastow
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Patent number: 6444539Abstract: A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads.Type: GrantFiled: February 15, 2001Date of Patent: September 3, 2002Assignees: Advanced Micro Devices, Inc., Fujitsu LimitedInventors: Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark Chang, Chi Chang, Hung-Sheng Chen
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Patent number: 6436778Abstract: A process for fabricating a semiconductor device 20 that includes providing semiconductor substrate 28 having a core region 24 and a peripheral gate region 26. The semiconductor substrate 28 has at least one shallow trench isolation region 30 and at least one nitrogen-contaminated region 36 in the peripheral gate region 26. A tunnel oxide layer 34 overlies the semiconductor substrate 28 and a first polysilicon layer 38 overlies the tunnel oxide layer 34 in the core region 24. An ONO layer 40 overlies the first polysilicon layer 38 in the core region 24. The process further includes growing a sacrificial oxide layer 42 overlying the nitrogen-contaminated region 36 in the peripheral gate region 26, wherein oxygen from within the sacrificial oxide layer 42 diffuses into the nitrogen-contaminated region 36 and forms silicon dioxide.Type: GrantFiled: June 12, 2001Date of Patent: August 20, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Hao Fang, Yue-song He
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Publication number: 20020106852Abstract: For fabricating a flash memory cell on a semiconductor substrate, a channel dopant is implanted into the semiconductor substrate. The concentration of the channel dopant in the semiconductor substrate from the implantation process is less than about 4×1013/cm2. A source line mask is formed over the substrate, and the source line mask has an opening to expose a source line of the semiconductor substrate. A source line dopant of a first conductivity type is implanted into the exposed source line of the semiconductor substrate. The source line mask is then removed from the semiconductor substrate. A drain mask is formed over the semiconductor substrate, and the drain mask has an opening to expose a drain region of the semiconductor substrate. A drain dopant of a second conductivity type is implanted into the exposed drain region of the semiconductor substrate. A channel region of the semiconductor substrate is disposed between the source line and the drain region.Type: ApplicationFiled: October 30, 2001Publication date: August 8, 2002Inventors: Yue-Song He, Sameer Haddad, Richard Fastow, Chi Chang, Zhigang Wang, Sheung-Hee Park
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Patent number: 6380033Abstract: In one embodiment, the present invention relates to a method of forming a NAND type flash memory device capable of more than about 1×105 program/erase cycles without significant read disturb problems involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N2O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layeType: GrantFiled: September 20, 1999Date of Patent: April 30, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Yue-song He, Kent K. Chang, Allen U. Huang
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Patent number: 6309949Abstract: A process for forming an isolation region while substantially eliminating weak oxide effects, comprising the steps of obtaining a semiconductor substrate patterned with a plurality of mesas with sidewalls, each of the mesas comprising at least a first insulator layer and a second different insulated layer thereover, forming a trench between the mesas into the semiconductor substrate, removing a lateral portion of the first insulator layer exposed at the sidewalls of the mesas to thereby undercut the second insulator layer at its sidewall edges, forming an oxide layer on exposed areas of the semiconductor substrate below the undercut of the second insulator layer, and filling the trench with an insulator material.Type: GrantFiled: November 16, 1999Date of Patent: October 30, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Yue Song He, Yowjuang William Liu
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Patent number: 6306707Abstract: In the manufacture of an EPROM or EEPROM semiconductor device that includes a core region and a peripheral region, a nitride layer is formed over the core region and peripheral region, and an oxide layer is formed over the nitride layer. A layer of photoresist is provided over the oxide layer and is patterned to expose a portion of the oxide layer overlying the core region. A wet etch step is undertaken to remove the exposed portion of the oxide layer, using the patterned photoresist as a mask, and leaving exposed a portion of the nitride layer overlying the core region. After removal of the photoresist, the exposed portion of the nitride layer is etched by a wet etch step with hot phosphoric acid, using the pattered oxide layer as a mask.Type: GrantFiled: November 20, 2000Date of Patent: October 23, 2001Assignee: Adanced Micro Devices, Inc.Inventors: John Foster, Yue-Song He, Jiahua Huang
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Patent number: 6284602Abstract: In one embodiment, the present invention relates to a method of forming a NAND type flash memory device involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; annealing the first oxide layer and the second oxide layer under an inert gas and at least one of N2O and NO for a period of time from about 1 minute to about 15 minutes; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphousType: GrantFiled: September 20, 1999Date of Patent: September 4, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Yue-song He, Kent K. Chang, Allen U. Huang
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Patent number: 6232646Abstract: A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads.Type: GrantFiled: May 20, 1998Date of Patent: May 15, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Yu Sun, Angela T. Hui, Yue-Song He, Tatsuya Kajita, Mark Chang, Chi Chang, Hung-Sheng Chen
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Patent number: 6177316Abstract: An improved method for fabricating a NAND-type memory cell structure. The present invention forgoes providing a contact mask implantation process prior to deposition of a metal barrier layer, which is a typical order of processing the NAND-type memory cell. Instead, in the present invention, the metal barrier layer is deposited on a core area of the NAND-type memory cell prior to contact mask implantation. Thereafter, the contact mask implantation process is performed on the structure in a conventional manner.Type: GrantFiled: October 5, 1999Date of Patent: January 23, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Yue-Song He, Kent K. Chang, John J. Wang
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Patent number: 6153470Abstract: A method of forming floating gate to improve tunnel oxide reliability for flash memory devices. A substrate having a source, drain, and channel regions is provided. A tunnel oxide layer is formed over the substrate. A floating gate is formed over the tunnel oxide and the channel region, the floating gate being multi-layered and having a second layer sandwiched between a first layer and a third layer. The first layer of the floating gate overlying the tunnel oxide layer includes an undoped or lightly doped material. The second layer is highly-doped. The third layer is in direct contact with a dielectric layer, e.g., an oxide-nitride-oxide stack, and is made of an undoped or lightly doped material. A dielectric material is formed over the floating gate and a control gate is formed over the dielectric material.Type: GrantFiled: August 12, 1999Date of Patent: November 28, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Yue-Song He, Kent K. Chang, Jiahua Huang