Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

Abstract: Disclosed are methods of forming a CMOS device. One non-limiting method may include providing a gate structure atop a substrate, and forming a first spacer over the gate structure. The method may include removing the first spacer from just an upper portion of the gate structure by performing an angled reactive ion etch or angled implantation disposed at a non-zero angle of inclination with respect to a perpendicular to a plane of the substrate. The method may further include forming a second spacer over the upper portion of the gate structure and the first spacer along a lower portion of the gate structure. A thickness of the first spacer and the second spacer along the lower portion of the gate structure may be greater than a thickness of the second spacer along the upper portion of the gate structure.

Abstract: Some embodiments include a construction having a horizontally-extending layer of fluorocarbon material over a semiconductor construction. Some embodiments include methods of filling openings that extend into a semiconductor construction. The methods may include, for example, printing the material into the openings or pressing the material into the openings. The construction may be treated so that surfaces within the openings adhere the material provided within the openings while surfaces external of the openings do not adhere the material. In some embodiments, the surfaces external of the openings are treated to reduce adhesion of the material.

Abstract: The present disclosure relates to a method for creating regions of different device types. The substrate is divided into a first device region and a second device region. A target etch layer is formed on a substrate. A bottom mandrel layer is formed on the target etch layer. A plurality of first pillars of a top mandrel material is formed on the bottom mandrel layer in the first device region, having a first pitch. A plurality of first spacers is formed along sidewalls of each of the plurality of first pillars. An optical planarization layer (OPL) is formed over the plurality of first pillars, the plurality of first spacers, and a top surface of the bottom mandrel layer in the first device region. A plurality of second pillars of the top mandrel material is formed on the bottom mandrel layer in the second device region, having a second pitch.

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

Abstract: Some embodiments include a construction having a horizontally-extending layer of fluorocarbon material over a semiconductor construction. Some embodiments include methods of filling openings that extend into a semiconductor construction. The methods may include, for example, printing the material into the openings or pressing the material into the openings. The construction may be treated so that surfaces within the openings adhere the material provided within the openings while surfaces external of the openings do not adhere the material. In some embodiments, the surfaces external of the openings are treated to reduce adhesion of the material.

Abstract: Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.

Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.

Abstract: A method of forming a three-dimensional transistor device. The method may include providing a fin array on a substrate, the fin array comprising a plurality of fin structures, formed from a monocrystalline semiconductor, and disposed subjacent to a hard mask layer. The method may include directing angled ions at the fin array, wherein the angled ions form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate. The angled ions may etch the plurality of fin structures to form a stack of isolated nanowires, within a given fin structure.

Abstract: The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires.

Abstract: A method may include forming in a substrate a first array of a first material of first linear structures, interspersed with a second array of a second material, of second linear structures, the first and second linear structures elongated along a first axis. The method may include generating a chop pattern in the first layer, comprising a third linear array, interspersed with a fourth linear array. The third and fourth linear arrays may be elongated along a second axis, forming a non-zero angle of incidence with respect to the first axis. The third linear array may include alternating portions of the first and second material, while the fourth linear array comprises an array of cavities, arranged within the patterning layer. The method may include elongating a first set of cavities along the first axis, to form a first set of elongated cavities bounded by the first material.

Abstract: The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires.

Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.

Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.

Abstract: Methods for forming semiconductor devices herein may include forming a trench in a substrate layer, wherein a hardmask is disposed atop the substrate layer, and implanting the trench at an angle relative to a top surface of the hardmask. The method may further include forming an oxide layer within the trench, wherein a thickness of the oxide layer along a bottom portion of the trench is greater than a thickness of the oxide layer along an upper portion of the trench.

Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.

Abstract: Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with dielectric material comprising silicon, oxygen and carbon. The carbon is present to a concentration within a range of from about 3 atomic percent to about 20 atomic percent. Some embodiments include a method of providing dielectric fill across a semiconductor construction having an opening extending therein. The semiconductor construction has an upper surface proximate the opening. The method includes forming photopatternable dielectric material within the opening and across the upper surface, and exposing the photopatternable dielectric material to patterned actinic radiation.

Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.

Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.