Patents by Inventor Soo-Nam Jung
Soo-Nam Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960408Abstract: A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.Type: GrantFiled: November 7, 2022Date of Patent: April 16, 2024Assignee: SK HYNIX INC.Inventors: Dong Hyuk Kim, Tae Sung Park, Sang Hyun Sung, Sung Lae Oh, Soo Nam Jung
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Publication number: 20230401157Abstract: A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.Type: ApplicationFiled: November 7, 2022Publication date: December 14, 2023Inventors: Dong Hyuk KIM, Tae Sung PARK, Sang Hyun SUNG, Sung Lae OH, Soo Nam JUNG
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Publication number: 20230230920Abstract: A semiconductor device includes a first connection pattern; a bit line disposed over the first connection pattern in a vertical direction; and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern, and formed as an island when viewed along the vertical direction. A predetermined number of the bit-line contact pads are spaced apart from each other by a predetermined distance in a first direction, when viewed along the vertical direction.Type: ApplicationFiled: March 29, 2023Publication date: July 20, 2023Inventors: Dong Hyuk KIM, Sung Lae OH, Tae Sung PARK, Soo Nam JUNG
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Patent number: 11646265Abstract: A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes a first connection pattern, a bit line disposed over the first connection pattern in a vertical direction, and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern so that the bit-line contact pad, and formed as an island when viewed along the vertical direction.Type: GrantFiled: October 23, 2020Date of Patent: May 9, 2023Assignee: SK hynix Inc.Inventors: Dong Hyuk Kim, Sung Lae Oh, Tae Sung Park, Soo Nam Jung
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Patent number: 11563030Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.Type: GrantFiled: June 9, 2021Date of Patent: January 24, 2023Assignee: SK hynix Inc.Inventors: Sung-Lae Oh, Dong-Hyuk Kim, Tae-Sung Park, Soo-Nam Jung, Chang-Woon Choi
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Patent number: 11488976Abstract: A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.Type: GrantFiled: December 15, 2020Date of Patent: November 1, 2022Assignee: SK hynix Inc.Inventors: Sung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
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Semiconductor memory device having three-dimensional structure and method for manufacturing the same
Patent number: 11342353Abstract: A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.Type: GrantFiled: February 1, 2020Date of Patent: May 24, 2022Assignee: SK hynix Inc.Inventors: Sung Lae Oh, Jin Ho Kim, Sang Woo Park, Sang Hyun Sung, Soo Nam Jung, Chang Woon Choi -
Semiconductor memory device having three-dimensional structure and method for manufacturing the same
Patent number: 11315935Abstract: A semiconductor memory device includes a stack disposed over a first substrate; an etch barrier including a plurality of dummy channels which pass through the stack and surround a coupling region; and a plurality of channels passing through the stack in a cell region outside the coupling region. The stack has a structure in which first dielectric layers and second dielectric layers are alternately stacked, inside the coupling region, and has a structure in which the first dielectric layers and electrode layers are alternately stacked, outside the coupling region.Type: GrantFiled: March 5, 2020Date of Patent: April 26, 2022Assignee: SK hynix Inc.Inventors: Tae Sung Park, Sung Lae Oh, Dong Hyuk Kim, Soo Nam Jung -
Patent number: 11232840Abstract: A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other.Type: GrantFiled: July 17, 2020Date of Patent: January 25, 2022Assignee: SK hynix Inc.Inventors: Sung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
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Patent number: 11211328Abstract: A semiconductor memory device includes a memory chip defined with a first pad on one surface thereof; and a circuit chip defined with a second pad which is coupled with the first pad, on one surface thereof bonded with the one surface of the memory chip. The memory chip comprising: a memory cell array; a bit line disposed in a first wiring layer between the one surface and the memory cell array, and separated into a first bit line section and a second bit line section; and a power pad disposed in a space between the first bit line section and the second bit line section in the first wiring layer, and coupled with the first pad.Type: GrantFiled: January 20, 2020Date of Patent: December 28, 2021Assignee: SK hynix Inc.Inventors: Sung-Lae Oh, Dong-Hyuk Kim, Soo-Nam Jung
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Publication number: 20210296362Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.Type: ApplicationFiled: June 9, 2021Publication date: September 23, 2021Inventors: Sung-Lae OH, Dong-Hyuk KIM, Tae-Sung PARK, Soo-Nam JUNG, Chang-Woon CHOI
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Publication number: 20210287982Abstract: A semiconductor device is disclosed, which relates to a three-dimensional (3D) semiconductor memory device. The semiconductor device includes a first connection pattern, a bit line disposed over the first connection pattern in a vertical direction, and a bit-line contact pad, disposed in a first layer between the bit line and the first connection pattern to electrically couple the bit line to the first connection pattern so that the bit-line contact pad, and formed as an island when viewed along the vertical direction.Type: ApplicationFiled: October 23, 2020Publication date: September 16, 2021Inventors: Dong Hyuk KIM, Sung Lae OH, Tae Sung PARK, Soo Nam JUNG
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Patent number: 11114152Abstract: A semiconductor memory device includes a memory cell; and a page buffer including a sensing circuit that is coupled to the memory cell through a bit line. The page buffer includes a first transistor included in the sensing circuit; and a second transistor not included in the sensing circuit. A cross-sectional dimension of a first contact which is coupled to the first transistor and a cross-sectional dimension of a second contact which is coupled to the second transistor are different from each other. The cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.Type: GrantFiled: September 2, 2020Date of Patent: September 7, 2021Assignee: SK hynix Inc.Inventors: Dong Hyuk Kim, Sung Lae Oh, Yeong Taek Lee, Tae Sung Park, Soo Nam Jung
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Patent number: 11107521Abstract: A semiconductor memory device may include a memory cell array; and a cache latch circuit that exchanges data with the memory cell array through a plurality of bit lines extended in a second direction crossing a first direction. The memory cell array may include a plurality of cache latches arranged in a plurality of columns in the first direction and in a plurality of rows in the second direction. Each of the cache latches may be coupled to any one of a plurality of input/output (IO) pins. Cache latches coupled to the IO pins at the same time may constitute one IO cache latch unit. The cache latches included in the one IO cache latch unit may be arranged in 2×2 array units.Type: GrantFiled: February 7, 2020Date of Patent: August 31, 2021Assignee: SK hynix Inc.Inventors: Sung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
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Patent number: 11101002Abstract: A semiconductor memory device includes a memory cell array; a page buffer circuit including a plurality of page buffers which are coupled to the memory cell array through a plurality of bit lines which extend in a second direction intersecting with a first direction; and a cache latch circuit including a plurality of cache latches which are coupled to the plurality of page buffers. The plurality of cache latches have a two-dimensional arrangement in the first direction and the second direction. Among the plurality of cache latches, an even cache latch and an odd cache latch which share a data line and an inverted data line are disposed adjacent to each other in the first direction.Type: GrantFiled: March 5, 2020Date of Patent: August 24, 2021Assignee: SK hynix Inc.Inventors: Sung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
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Patent number: 11094382Abstract: A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.Type: GrantFiled: May 27, 2020Date of Patent: August 17, 2021Assignee: SK hynix Inc.Inventors: Sung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
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Publication number: 20210241835Abstract: A semiconductor device including a page buffer is disclosed, which reduces the number of lines of the page buffer. The semiconductor device includes a plurality of bit lines, classified into a first group and a second group, that are arranged alternating, a first page buffer circuit coupled to the plurality of bit lines and a plurality of connection lines corresponding to the plurality of bit lines, and a second page buffer circuit coupled to the plurality of connection lines. Each of the first group and the second group includes a plurality of bit-line pairs classified into odd bit lines and even bit lines. The plurality of connection lines includes odd connection lines and even connection lines, and odd connection lines corresponding to the odd bit lines are arranged contiguous to each other, and even connection lines corresponding to the even bit lines are arranged contiguous to each other.Type: ApplicationFiled: July 17, 2020Publication date: August 5, 2021Inventors: Sung Lae OH, Dong Hyuk KIM, Tae Sung PARK, Soo Nam JUNG
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Publication number: 20210217479Abstract: A semiconductor memory device includes a plurality of page buffers defined in active regions of a substrate; and a plurality of wiring lines disposed over the page buffers, and coupled to the page buffers through contacts. The plurality of wiring lines may include contact portions which are coupled with the contacts, respectively. The plurality of wiring lines may be configured into a bent shape such that the contact portions are offset toward center lines of the active regions.Type: ApplicationFiled: May 27, 2020Publication date: July 15, 2021Inventors: Sung Lae OH, Dong Hyuk KIM, Tae Sung PARK, Soo Nam JUNG
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Patent number: 11063061Abstract: A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.Type: GrantFiled: July 18, 2019Date of Patent: July 13, 2021Assignee: SK hynix Inc.Inventors: Sung-Lae Oh, Dong-Hyuk Kim, Tae-Sung Park, Soo-Nam Jung, Chang-Woon Choi
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Publication number: 20210143173Abstract: A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.Type: ApplicationFiled: December 15, 2020Publication date: May 13, 2021Inventors: Sung Lae OH, Dong Hyuk KIM, Tae Sung PARK, Soo Nam JUNG