Patents by Inventor Soon Wei Wang
Soon Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11908699Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.Type: GrantFiled: April 25, 2022Date of Patent: February 20, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Patent number: 11901184Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.Type: GrantFiled: April 13, 2022Date of Patent: February 13, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Patent number: 11894234Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.Type: GrantFiled: July 19, 2022Date of Patent: February 6, 2024Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Patent number: 11721654Abstract: A method includes attaching semiconductor die to a carrier between copper pillars, covering with molding, backside grinding to expose first ends of the pillars and backside drain contacts of the die, and applying a layer of conductive material to electrically connect the first ends of the pillars and the backside drain contacts. The method further includes cutting grooves in the conductive material to isolate adjacent die, removing the carrier to expose second ends of the copper pillars in place in the molding, applying another layer of conductive material to electrically connect the second ends of the copper pillars and source contacts of adjacent die, singulating individual MCM packages each including a first die and a second die with a source of the first die connected to a drain of the second die via one of the copper pillars left in place in the molding.Type: GrantFiled: February 22, 2021Date of Patent: August 8, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Nurul Nadiah Manap, Shutesh Krishnan, Soon Wei Wang
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Publication number: 20230073773Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.Type: ApplicationFiled: November 16, 2022Publication date: March 9, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hui Min LER, Soon Wei WANG, Chee Hiong CHEW
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Publication number: 20230073330Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.Type: ApplicationFiled: November 17, 2022Publication date: March 9, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hui Min LER, Soon Wei WANG, Chee Hiong CHEW
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Patent number: 11532539Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.Type: GrantFiled: December 29, 2020Date of Patent: December 20, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hui Min Ler, Soon Wei Wang, Chee Hiong Chew
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Patent number: 11508679Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.Type: GrantFiled: October 12, 2020Date of Patent: November 22, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Soon Wei Wang, Chee Hiong Chew, Francis J. Carney
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Publication number: 20220351978Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
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Publication number: 20220351977Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.Type: ApplicationFiled: July 19, 2022Publication date: November 3, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. CARNEY, Yusheng LIN, Michael J. SEDDON, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
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Publication number: 20220301876Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.Type: ApplicationFiled: June 9, 2022Publication date: September 22, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Francis J. CARNEY, Eiji KUROSE, Chee Hiong CHEW, Soon Wei WANG
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Publication number: 20220246434Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.Type: ApplicationFiled: April 25, 2022Publication date: August 4, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
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Patent number: 11404277Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.Type: GrantFiled: May 20, 2020Date of Patent: August 2, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Yusheng Lin, Michael J. Seddon, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Patent number: 11404276Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.Type: GrantFiled: May 20, 2020Date of Patent: August 2, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Publication number: 20220238342Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. SEDDON, Francis J. CARNEY, Chee Hiong CHEW, Soon Wei WANG, Eiji KUROSE
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Publication number: 20220208658Abstract: Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Hui Min LER, Soon Wei WANG, Chee Hiong CHEW
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Patent number: 11361970Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.Type: GrantFiled: April 29, 2020Date of Patent: June 14, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Francis J. Carney, Eiji Kurose, Chee Hiong Chew, Soon Wei Wang
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Patent number: 11348796Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.Type: GrantFiled: May 20, 2020Date of Patent: May 31, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Patent number: 11342189Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.Type: GrantFiled: August 5, 2020Date of Patent: May 24, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Michael J. Seddon, Francis J. Carney, Chee Hiong Chew, Soon Wei Wang, Eiji Kurose
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Publication number: 20210183799Abstract: A method includes attaching semiconductor die to a carrier between copper pillars, covering with molding, backside grinding to expose first ends of the pillars and backside drain contacts of the die, and applying a layer of conductive material to electrically connect the first ends of the pillars and the backside drain contacts. The method further includes cutting grooves in the conductive material to isolate adjacent die, removing the carrier to expose second ends of the copper pillars in place in the molding, applying another layer of conductive material to electrically connect the second ends of the copper pillars and source contacts of adjacent die, singulating individual MCM packages each including a first die and a second die with a source of the first die connected to a drain of the second die via one of the copper pillars left in place in the molding.Type: ApplicationFiled: February 22, 2021Publication date: June 17, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Nurul Nadiah MANAP, Shutesh KRISHNAN, Soon Wei WANG