Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Abstract: A multi-chip module (MCM) includes a molded body portion having a first outer surface and a second outer surface. A conductive layer defines at least a portion of the first outer surface A conductive connection layer portion is disposed outside of the second outer surface of the molded body portion. A first semiconductor die and a second semiconductor die are disposed between the conductive layer and the conductive connection layer, and first molding portion is disposed between the first semiconductor die and the second semiconductor die. The first molding portion extends between the first outer surface and the second outer surface of the molded body portion. A conductive pillar is electrically coupled to the conductive layer defining at least a portion of the first outer surface and the conductive connection layer portion disposed outside of the second outer surface.

Abstract: Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.

Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.

Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and into the plurality of notches; forming a cavity into each of a plurality of semiconductor die included in the semiconductor substrate; applying a backmetal into the cavity in each of the plurality of semiconductor die included in the semiconductor substrate; and singulating the semiconductor substrate through the organic material into a plurality of semiconductor packages.

Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

Abstract: A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

Abstract: Implementations of semiconductor packages may include: a lead frame having at least one corner lead, the at least one corner lead positioned where two edges of the package meet, and the at least one lead having a half etch on a first portion of the lead and a half etch on a second portion of the lead. The first portion may extend internally into the package to create a mechanical mold compound lock between a mold compound of the package and the lead. The second portion may be located on at least one of the two edges of the package.

Abstract: Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; forming an organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; stress relief etching the second side of the semiconductor substrate; applying a backmetal over the second side of the semiconductor substrate; removing one or more portions of the backmetal through jet ablating the second side of the semiconductor substrate; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Abstract: Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.

Abstract: Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

Abstract: Implementations of a semiconductor device may include a semiconductor die comprising a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface, and a permanent die support structure coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The thickness may be between 0.1 microns and 125 microns. The warpage of the semiconductor die may be less than 200 microns.

Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.

Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.

Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.