Patents by Inventor Sou-Chi Chang

Sou-Chi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11063131
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • Publication number: 20210167182
    Abstract: A integrated circuit structure comprises a fin extending from a substrate. The fin comprises source and drain regions and a channel region between the source and drain regions. A multilayer high-k gate dielectric stack comprises at least a first high-k material and a second high-k material, the first high-k material extending conformally over the fin over the channel region, and the second high-k material conformal to the first high-k material, wherein either the first high-k material or the second high-k material has a modified material property different from the other high-k material, wherein the modified material property comprises at least one of ferroelectricity, crystalline phase, texturing, ordering orientation of the crystalline phase or texturing to a specific crystalline direction or plane, strain, surface roughness, and lattice constant and combinations thereof. A gate electrode ix over and on a topmost high-k material in the multilayer high-k gate dielectric stack.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Seung Hoon SUNG, Ashish Verma PENUMATCHA, Sou-Chi CHANG, Devin MERRILL, I-Cheng TUNG, Nazila HARATIPOUR, Jack T. KAVALIEROS, Ian A. YOUNG, Matthew V. METZ, Uygar E. AVCI, Chia-Ching LIN, Owen LOH, Shriram SHIVARAMAN, Eric Charles MATTSON
  • Publication number: 20210111179
    Abstract: A memory device comprises a bitline along a first direction. A wordline is along a second direction orthogonal to the first direction. An access transistor is coupled to the bitline and the wordline. A first ferroelectric capacitor is vertically aligned with and coupled to the access transistor. A second ferroelectric capacitor is vertically aligned with the first ferroelectric capacitor and coupled to the access transistor, wherein both the first ferroelectric capacitor and the second ferroelectric capacitor are controlled by the access transistor.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Shriram SHIVARAMAN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Nazila HARATIPOUR, Uygar E. AVCI
  • Publication number: 20200403081
    Abstract: Described is a transistor which includes: a source region; a drain region; and a gate region between the source and drain regions, wherein the gate region comprises: high-K dielectric material between spacers such that the high-K dielectric material is recessed; and metal electrode on the recessed high-K dielectric material. The gate recessed gate dielectric allows for using thick gate dielectric even with much advanced process technology nodes (e.g., 7 nm and below).
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: Seung Hoon Sung, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Matthew Metz, Michael Harper, Jack Kavalieros, Uygar Avci, Ian Young
  • Publication number: 20200395435
    Abstract: An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: INTEL CORPORATION
    Inventors: NAZILA HARATIPOUR, CHIA-CHING LIN, SOU-CHI CHANG, IAN A. YOUNG, UYGAR E. AVCI, JACK T. KAVALIEROS
  • Publication number: 20200395460
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by providing tensile stress along a plane (e.g., x-axis) of a ferroelectric or anti-ferroelectric material of the ferroelectric/anti-ferroelectric based capacitor. Tensile stress is provided by a spacer comprising metal, semimetal, or oxide (e.g., metal or oxide of one or more of: Al, Ti, Hf, Si, Ir, or N). The tensile stress provides polar orthorhombic phase to the ferroelectric material and tetragonal phase to the anti-ferroelectric material. As such, memory window and reliability of the ferroelectric/anti-ferroelectric oxide thin film improves.
    Type: Application
    Filed: June 13, 2019
    Publication date: December 17, 2020
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, Sou-Chi Chang, Chia-Ching Lin, Jack Kavalieros, Uygar Avci, Ian Young
  • Patent number: 10861861
    Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 8, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Sou-Chi Chang, Uygar E. Avci, Ian A. Young
  • Publication number: 20200312950
    Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Nazila HARATIPOUR, Chia-Ching LIN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Owen LOH, Mengcheng LU, Seung Hoon SUNG, Ian A. YOUNG, Uygar AVCI, Jack T. KAVALIEROS
  • Publication number: 20200312978
    Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Jack KAVALIEROS, Ian YOUNG, Matthew METZ, Uygar AVCI, Chia-Ching LIN, Owen LOH, Seung Hoon SUNG, Aditya KASUKURTI, Sou-Chi CHANG, Tanay GOSAVI, Ashish Verma PENUMATCHA
  • Publication number: 20200312949
    Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 1, 2020
    Inventors: Nazila HARATIPOUR, Chia-Ching LIN, Sou-Chi CHANG, Ashish Verma PENUMATCHA, Owen LOH, Mengcheng LU, Seung Hoon SUNG, Ian A. YOUNG, Uygar AVCI, Jack T. KAVALIEROS
  • Publication number: 20200286687
    Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Nazila Haratipour, Seung Hoon Sung, Ashish Verma Penumatcha, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286685
    Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286984
    Abstract: Disclosed herein are capacitors with ferroelectric or antiferroelectric (FE/AFE) material and dielectric material, as well as related methods and devices. In some embodiments, a capacitor may include two electrodes, a layer of FE/AFE material between the electrodes, and a layer of dielectric material between the electrodes.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Sou-Chi Chang, Chia-Ching Lin, Ashish Verma Penumatcha, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286686
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200287017
    Abstract: A gate stack is described that uses anti-ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2) or ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2, perovskite ferroelectric such as NH4H2PO4, KH2PO4, LiNb03, LiTaO3, BaTiO3, PbTiO3, Pb (Zr,Ti) O3, (Pb,La)TiO3, and (Pb,La)(Zr,Ti)O3) which reduces write voltage, improves endurance, and increases retention. The gate stack of comprises strained anti-FE or FE material and depolarized anti-FE or FE. The endurance of the FE transistor is further improved by using a higher K (constant) dielectric (e.g., SiO2, Al2O3, HfO2, Ta2O3, La2O3) in the gate stack. High K effects may also be achieved by depolarizing the FE or FE oxide in the transistor gate stack.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Sou-Chi CHANG, Chia-Chang LIN, Seung Hoon SUNG, Ashish Verma PENUMATCHA, Nazila HARATIPOURA, Owen LOH, Jack KAVALIEROS, Uygar AVCI, Ian YOUNG
  • Publication number: 20200212055
    Abstract: A memory device comprises a trench within an insulating layer. A bottom electrode material is along sidewalls and a bottom of the trench, the bottom electrode material conformal to a top surface of the insulating layer. A ferroelectric material is conformal to the bottom electrode. A top electrode material is conformal to the ferroelectric material, wherein the bottom electrode material, the ferroelectric material and the top electrode material all extend above and across the top surface of the insulating layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: Chia-Ching LIN, Sasikanth MANIPATRUNI, Tanay GOSAVI, Dmitri NIKONOV, Sou-Chi CHANG, Uygar E. AVCI, Ian A. YOUNG
  • Publication number: 20200194444
    Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Sou-Chi Chang, Uygar E. Avci, Ian A. Young
  • Publication number: 20200091308
    Abstract: A capacitor is provided which comprises: a first structure comprising metal; a second structure comprising metal; and a third structure between the first and second structures, wherein the third structure comprises an improper ferroelectric material. In some embodiments, a field effect transistor (FET) is provided which comprises: a substrate; a source and drain adjacent to the substrate; and a gate stack between the source and drain, wherein the gate stack includes: a dielectric; a first structure comprising improper ferroelectric material, wherein the first structure is adjacent to the dielectric; and a second structure comprising metal, wherein the second structure is adjacent to the first structure.
    Type: Application
    Filed: September 13, 2018
    Publication date: March 19, 2020
    Applicant: Intel Corporation
    Inventors: Sasikanth Manipatruni, Uygar Avci, Sou-Chi Chang, Ian Young
  • Publication number: 20190393232
    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Sou-Chi CHANG, Uygar E. AVCI, Daniel H. MORRIS, Seiyon KIM, Ashish V. PENUMATCHA, Ian A. YOUNG
  • Publication number: 20190386120
    Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as., EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.
    Type: Application
    Filed: June 14, 2018
    Publication date: December 19, 2019
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Sou-Chi Chang, Dmitri Nikonov, Ian A. Young