Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

Abstract: A gate stack is described that uses anti-ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2) or ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2, perovskite ferroelectric such as NH4H2PO4, KH2PO4, LiNb03, LiTaO3, BaTiO3, PbTiO3, Pb (Zr,Ti) O3, (Pb,La)TiO3, and (Pb,La)(Zr,Ti)O3) which reduces write voltage, improves endurance, and increases retention. The gate stack of comprises strained anti-FE or FE material and depolarized anti-FE or FE. The endurance of the FE transistor is further improved by using a higher K (constant) dielectric (e.g., SiO2, Al2O3, HfO2, Ta2O3, La2O3) in the gate stack. High K effects may also be achieved by depolarizing the FE or FE oxide in the transistor gate stack.

Abstract: Described is an ultra-dense ferroelectric memory. The memory is fabricated using a patterning method by that applies atomic layer deposition with selective dry and/or wet etch to increase memory density at a given via opening. A ferroelectric capacitor in one example comprises: a first structure (e.g., first electrode) comprising metal; a second structure (e.g., a second electrode) comprising metal; and a third structure comprising ferroelectric material, wherein the third structure is between and adjacent to the first and second structures, wherein a portion of the third structure is interdigitated with the first and second structures to increase surface area of the third structure. The increased surface area allows for higher memory density.

Abstract: Disclosed herein are capacitors with ferroelectric or antiferroelectric (FE/AFE) material and dielectric material, as well as related methods and devices. In some embodiments, a capacitor may include two electrodes, a layer of FE/AFE material between the electrodes, and a layer of dielectric material between the electrodes.

Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

Abstract: A memory device comprises a trench within an insulating layer. A bottom electrode material is along sidewalls and a bottom of the trench, the bottom electrode material conformal to a top surface of the insulating layer. A ferroelectric material is conformal to the bottom electrode. A top electrode material is conformal to the ferroelectric material, wherein the bottom electrode material, the ferroelectric material and the top electrode material all extend above and across the top surface of the insulating layer.

Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.

Abstract: A capacitor is provided which comprises: a first structure comprising metal; a second structure comprising metal; and a third structure between the first and second structures, wherein the third structure comprises an improper ferroelectric material. In some embodiments, a field effect transistor (FET) is provided which comprises: a substrate; a source and drain adjacent to the substrate; and a gate stack between the source and drain, wherein the gate stack includes: a dielectric; a first structure comprising improper ferroelectric material, wherein the first structure is adjacent to the dielectric; and a second structure comprising metal, wherein the second structure is adjacent to the first structure.

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a capacitor. The capacitor may include a first electrode, a second electrode, and a paraelectric layer between the first electrode and the second electrode. A first interface with a first work function exists between the paraelectric layer and the first electrode. A second interface with a second work function exists between the paraelectric layer and the second electrode. The paraelectric layer may include a ferroelectric material or an anti-ferroelectric material. A built-in electric field associated with the first work function and the second work function may exist between the first electrode and the second electrode. The built-in electric field may be at a voltage value where the capacitor may operate at a center of a memory window of a polarization-voltage hysteresis loop of the capacitor. Other embodiments may be described and/or claimed.

Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as., EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.