Structure Of Integrated Circuitry And A Method Of Forming A Conductive Via
A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.
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Embodiments disclosed herein pertain to structures of integrated circuitry and to methods of forming a conductive via.
BACKGROUNDMemory is one type of integrated circuitry, and is used in computer systems for storing data. Memory may be fabricated in one or more arrays of individual memory cells. Memory cells may be written to, or read from, using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines may conductively interconnect memory cells along columns of the array, and the access lines may conductively interconnect memory cells along rows of the array. Each memory cell may be uniquely addressed through the combination of a sense line and an access line.
Memory cells may be volatile, semi-volatile, or nonvolatile. Nonvolatile memory cells can store data for extended periods of time in the absence of power. Nonvolatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates, and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1”. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.
One type of memory cell has at least one transistor and at least one capacitor. In some such structures, one conductive via extends downwardly from a sense line to one source/drain region (e.g., a circuit node) of the transistor. Additionally, another conductive via may be laterally-adjacent the one conductive via and extend downwardly from a storage node of the capacitor to another source/drain region of the transistor. Unfortunately, parasitic capacitance exists laterally between the one conductive via and the other conductive via and can be 40 attofarads or more at a voltage delta between such vias of no greater than 1.1 volts. Such parasitic capacitance can adversely affect circuit performance. Parasitic capacitance laterally between conductive vias in other circuitry can also adversely affect circuit performance.
Embodiments of the invention encompass methods of forming a conductive via and a structure of integrated circuitry independent of method of manufacture. Method embodiments are initially described with reference to
Referring to
Base substrate 11 comprises semiconductor material 12 (e.g., appropriately, and variously, doped monocrystalline silicon), trench isolation regions 14 (e.g., silicon nitride and/or doped or undoped silicon dioxide), and active area regions 16 comprising suitably-doped semiconductor material 12. In one embodiment and as will be shown, structure 8 will comprise memory cells individually comprising a field effect transistor 25 and a capacitor (not shown in
Structures/constructions 28 have been fabricated above base substrate 11. The discussion proceeds with fabrication relative to a single structure in a method of forming a conductive via, although multiple such structures may be formed as is inherently shown in the figures. Structure 28 has been formed to comprise an elevationally-extending-conductive via 30 and a conductive line 32 electrically coupled to and crossing above conductive via 30. In one embodiment and as shown, individual conductive lines 32 are directly electrically coupled to and directly against tops 37 of conductive vias 30. Conductive line 32 comprises first conductive material 34 and conductive via 30 comprises second conductive material 36 of different composition from that of first conductive material 34. In one embodiment, first conductive material 34 comprises metal material (e.g., one or more of TiN, Ti, WN, WSix, etc.). An example thickness for conductive via 30 is 100 Angstroms to 200 Angstroms. An example thickness for conductive line 32 is 200 Angstroms to 400 Angstroms.
In one embodiment, second conductive material 36 comprises dopant(s) therein that is conductivity-increasing when within a semiconductor material (i.e., regardless of whether material 36 is a semiconductor material), and in one such embodiment source/drain region 26 comprises a circuit node comprising the semiconductor material. In one embodiment, conductive via 30 comprises conductively-doped semiconductor material that is conductively doped with the particular dopant(s). For example, and by way of example only, second conductive material 36 may comprise, consist essentially of, or consist of polysilicon that is conductively-doped with phosphorus (an n-type dopant), and material of source-drain region 26 (e.g., a circuit node) may comprise silicon that is conductively doped with phosphorus. Regardless, out-diffusion of dopant within second material 36 may occur into circuit node/source-drain region 26 inherent during substrate processing and/or be conducted by a dedicated anneal to achieve such. Alternately or additionally, and in one embodiment, second conductive material 36 may comprise metal material that may have the dopant(s) therein, and which may diffuse during processing into circuit node/source-drain region 26 (e.g., with such dopant(s) perhaps having no impact on the conductivity of second material 36 when such dopant is therein). Regardless, conductive via 30 has a bottom 38 that, in one embodiment, is directly against circuit node/source-drain region 26.
Conductive line 32 and conductive via 30 have opposing sides 35 and 33, respectively, in a vertical cross-section (e.g., the cross-section depicted by
Referring to
In one embodiment, the selectively forming comprises exposing structure 28 to a hydroxide to form first insulator material 44 to comprise an oxide. For example, where first conductive material 34 comprises metal material and second conductive material 36 comprises conductively-doped polysilicon, such act of selectively forming comprises exposing structure 28 to a hydroxide (e.g., liquid and/or vapor fluid comprising an ammonium-hydroxide such as tetra-methyl-ammonium-hydroxide, H2O2, O2, O3, H2O, etc.) to form silicon dioxide as first insulator material 44. A specific example is aqueous tetra-methyl-ammonium-hydroxide of volumetric concentration relative to water of about 20:1 to 2,000:1 at temperature of 20° C. to 500° C., sub-atmospheric pressure to greater than atmospheric pressure, and for 5 seconds to 10 hours to form first insulator material to comprise silicon dioxide.
First insulator material 44 may be considered as comprising opposing sides 47. Conductive via 30 may be considered as having an elevational length L from top 37 to bottom 38. In one embodiment, first insulator material 44 having lateral thickness of at least 40 Angstroms extends along at least a majority (i.e., more than 50%) of elevational length L of opposing sides 33 of conductive via 30 downwardly from aside top 37 of conductive via 30. In one embodiment and as shown, first insulator material 44 extends along less-than-all of elevational length L of opposing sides 33 of conductive via 30, for example not being along the depicted lowest-most portions of sidewalls 33. In one embodiment and as shown, first insulator material 44 is directly against conductive via 30.
Referring to
Referring to
In one embodiment, a pair of additional conductive vias is formed laterally outward of the second insulator material in the vertical cross-section. In one such embodiment, the additional vias are formed directly against the second insulator material in the vertical cross-section.
Referring to
Referring to
Referring to
Referring to
In one embodiment, structure 8 has parasitic capacitance laterally between conductor material 68 and conductive via 30 of less than 30 attofarads at a voltage delta between conductor material 68 and conductive via 30 of no greater than 1.1 volts. Such parasitic capacitance may be greater than 10 attofarads.
Embodiments of the invention also encompass constructions of integrated circuitry independent of method of manufacture. However, any of the structural attributes described above with respect to method embodiments may be found in structural aspects of the invention and vice versa. In one embodiment, a structure (e.g., 8) of integrated circuitry comprises an elevationally-extending-conductive via (e.g., 30) and a conductive line (e.g., 32) electrically coupled to and crossing above the conductive via. The conductive via has opposing sides (e.g., 33) in a vertical cross-section. First insulator material (e.g., 44) having k no greater than 4.0 is laterally outward of the opposing sides of the conductive via. The first insulator material has a lateral thickness of at least 40 Angstroms along the opposing sides of the conductive via in the vertical cross-section. Second insulator material (e.g., 56) having k greater than 4.0 is laterally outward of opposing sides (e.g., 47) of the first insulator material in the vertical cross-section. Conductor material (e.g., 68) is laterally outward of opposing sides (e.g., 66) of the second insulator material in the vertical cross-section. The conductor material on the opposing sides of the second insulator material has a respective bottom (e.g., 74). The first insulator material having lateral thickness of at least 40 Angstroms and k no greater than 4.0 extends lower than the bottoms of the conductor material on the opposing sides of the second insulator material.
Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.
In one embodiment, a structure (e.g., 8) of integrated circuitry comprises an elevationally-extending-conductive via (e.g., 30) and a conductive line (e.g., 32) electrically coupled to and crossing above the conductive via. The conductive via has opposing sides (e.g., 33) in a vertical cross-section. First insulator material (e.g., 44) having k no greater than 4.0 is laterally outward of the opposing sides of the conductive via along at least a majority of elevational-length of the opposing sides of the conductive via downwardly from aside a top (e.g., 37) of the conductive via. The first insulator material has a lateral thickness of at least 40 Angstroms along the opposing sides of the conductive via. Second insulator material (e.g., 56) having k greater than 4.0 is laterally outward of opposing sides (e.g., 47) of the first insulator material in the vertical cross-section. Conductor material (e.g., 68) is laterally outward of opposing sides (e.g., 66) of the second insulator material in the vertical cross-section.
Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.
In this document unless otherwise indicated, “elevational”, “higher”, “upper”, “lower”, “top”, “atop”, “bottom”, “above”, “below”, “under”, “beneath”, “up”, and “down” are generally with reference to the vertical direction. “Horizontal” refers to a general direction along a primary substrate surface and may be relative to which the substrate is processed during fabrication, and vertical is a direction generally orthogonal thereto. Further, “vertical” and “horizontal” as used herein are generally perpendicular directions relative one another and independent of orientation of the substrate in three-dimensional space. Additionally, “elevationally-extending” and “extending elevationally” refer to a direction that is angled away by at least 45° from horizontal. Further, “extend(ing) elevationally” and “elevationally-extending” with respect to a field effect transistor are with reference to orientation of the transistor's channel length along which current flows in operation between the source/drain regions. For bipolar junction transistors, “extend(ing) elevationally” and “elevationally-extending” are with reference to orientation of the base length along which current flows in operation between the emitter and collector.
Further, “directly above” requires at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).
Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Further, unless otherwise stated, each material may be formed using any suitable or yet-to-be-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.
Additionally, “thickness” by itself (no preceding directional adjective) is defined as the mean straight-line distance through a given material or region perpendicularly from a closest surface of an immediately-adjacent material of different composition or of an immediately-adjacent region. Additionally, the various materials or regions described herein may be of substantially constant thickness or of variable thicknesses. If of variable thickness, thickness refers to average thickness unless otherwise indicated, and such material or region will have some minimum thickness and some maximum thickness due to the thickness being variable. As used herein, “different composition” only requires those portions of two stated materials or regions that may be directly against one another to be chemically and/or physically different, for example if such materials or regions are not homogenous. If the two stated materials or regions are not directly against one another, “different composition” only requires that those portions of the two stated materials or regions that are closest to one another be chemically and/or physically different if such materials or regions are not homogenous. In this document, a material, region, or structure is “directly against” another when there is at least some physical touching contact of the stated materials, regions, or structures relative one another. In contrast, “over”, “on”, “adjacent”, “along”, and “against” not preceded by “directly” encompass “directly against” as well as construction where intervening material(s), region(s), or structure(s) result(s) in no physical touching contact of the stated materials, regions, or structures relative one another.
Herein, regions-materials-components are “electrically coupled” relative one another if in normal operation electric current is capable of continuously flowing from one to the other, and does so predominately by movement of subatomic positive and/or negative charges when such are sufficiently generated. Another electronic component may be between and electrically coupled to the regions-materials-components. In contrast, when regions-materials-components are referred to as being “directly electrically coupled”, no intervening electronic component (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) is between the directly electrically coupled regions-materials-components.
Additionally, “metal material” is any one or combination of an elemental metal, a mixture or an alloy of two or more elemental metals, and any conductive metal compound.
In this document, a selective etch or removal is an etch or removal where one material is removed relative to another stated and/or exposed material or materials at a rate of at least 2.0:1. Further, selectively growing or selectively forming is growing or forming one material relative to another stated and/or exposed material or materials at a rate of at least 2.0:1 for at least the first 100 Angstroms of growing or forming.
CONCLUSIONIn some embodiments, a method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section.
In some embodiments, a method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via comprising conductively-doped semiconductor material and a conductive line comprising metal material electrically coupled to and crossing above the conductive via. The conductive line and the conductive via respectively have opposing sides in a vertical cross-section. The structure is exposed to an ammonium-hydroxide-containing fluid to form an oxide-containing first insulator material having k no greater than 4.0 laterally outward of the opposing sides of the conductively-doped semiconductor material of the conductive via selectively relative to the metal material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. A nitride-containing insulative material is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. An oxide-containing-insulative material is formed laterally outward of opposing sides of the nitride-containing-insulative material in the vertical cross-section. A nitride-containing second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the oxide-containing-insulative material in the vertical cross-section. Insulating material is formed laterally outward of opposing sides of the oxide-containing-insulative material in the vertical cross-section above the second insulator material. Conductor material is formed laterally outward of opposing sides of the second insulator material in the vertical cross-section.
In some embodiments, a structure of integrated circuitry comprises an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive via has opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is laterally outward of the opposing sides of the conductive via. The first insulator material has a lateral thickness of at least 40 Angstroms along the opposing sides of the conductive via in the vertical cross-section. Second insulator material having k greater than 4.0 is laterally outward of opposing sides of the first insulator material in the vertical cross-section. Conductor material is laterally outward of opposing sides of the second insulator material in the vertical cross-section. The conductor material on the opposing sides of the second insulator material has a respective bottom. The first insulator material having lateral thickness of at least 40 Angstroms and k no greater than 4.0 extends lower than the bottoms of the conductor material on the opposing sides of the second insulator material.
In some embodiments, a structure of integrated circuitry comprises an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive via has opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is laterally outward of the opposing sides of the conductive via along at least a majority of elevational-length of the opposing sides of the conductive via downwardly from aside a top of the conductive via. The first insulator material has a lateral thickness of at least 40 Angstroms along the opposing sides of the conductive via. Second insulator material having k greater than 4.0 is laterally outward of opposing sides of the first insulator material in the vertical cross-section. Conductor material is laterally outward of opposing sides of the second insulator material in the vertical cross-section.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
Claims
1-20. (canceled)
21. A structure of integrated circuitry, comprising:
- a transistor comprising a pair of source/drain regions, a buried gate, and a channel region along the buried gate between the pair of source/drain regions;
- a first conductive via electrically coupled to and projecting from one of the pair of source/drain regions, the first conductive via having a first sidewall;
- a second conductive via electrically coupled to and projecting from the other of the pair of source/drain regions, the second conductive via having a second sidewall; and
- an insulative layer between the first sidewall of the first conductive via and the second sidewall of the second conductive via, the insulative layer comprising: first insulator material; second insulator material; third insulator material between the first and second insulator materials; and each of the first and second insulator materials having greater k than the third insulator material.
22. The structure of claim 21 wherein,
- each of the first and second insulator materials has k greater than 4.0; and
- the third insulator material has k no greater than 4.0.
23. The structure of claim 21 further comprising a conductive line electrically coupled to and crossing above the first conductive via.
24. The structure of claim 23 wherein the conductive line has a third sidewall, the insulative layer extending to cover the third sidewall of the conductive line.
25. The structure of claim 24 wherein the conductive line comprises a metal and the first conductive via comprises polycrystalline semiconductor material.
26. The structure of claim 21 wherein the insulative layer further comprises a fourth insulator material between the first and third insulator materials, each of the first and second insulator materials having greater k than the fourth insulator material.
27. The structure of claim 26 wherein,
- each of the first and second insulator materials has k greater than 4.0; and
- each of the third and fourth insulator materials has K no greater than 4.0.
28. The structure of claim 23 further comprising a capacitive element electrically coupled to the second conductive via.
29. A structure of integrated circuitry, comprising:
- a first semiconductor region having a first upper surface;
- a second semiconductor region having a second upper surface that is higher than the first upper surface of the first semiconductor region;
- a first conductive via electrically coupled to and projecting from the first semiconductor region, the first conductive via having a first sidewall;
- a second conductive via electrically coupled to and projecting from the second semiconductor region, the second conductive via having a second sidewall; and
- an isolation structure between the first and second conductive vias separating the first and second conductive vias from each other, the isolation structure comprising: first insulator material surrounding the first conductive via; and second insulator material intervening between the first insulator material and the second conductive via, the second insulator material comprising: third insulator material; fourth insulator material; fifth insulator material between the third and fourth insulator materials; and each of the third and fourth insulator materials having greater k than the fifth insulator material.
30. The structure of claim 29 wherein each of the third and fourth insulator materials has greater k than the first insulator material.
31. The structure of claim 30 wherein,
- each of the third and fourth insulator materials has k greater than 4.0; and
- each of the first and fifth insulator materials has k no greater than 4.0.
32. The structure of claim 29 wherein each of the first and second conductive vias comprises a polycrystalline semiconductor material.
33. The structure of claim 32 wherein the polycrystalline semiconductor material comprises polysilicon.
34. The structure of claim 29 further comprising a conductive line electrically coupled to and crossing above the first conductive via.
35. The structure of claim 34 wherein,
- the first insulator material terminates substantially at the first upper surface of the first conductive via; and
- the second insulator material extends to cover a sidewall of the conductive line.
36. The structure of claim 35 wherein,
- the conductive line has a third upper surface; and
- the second supper surface of the second conductive via is between the first upper surface of the first conductive via and the third upper surface of the conductive line.
37. The structure of claim 34 wherein the conductive line is different in material from each of the first and second conductive vias.
38. The structure of claim 29 wherein,
- the second insulator material further comprises sixth insulator material between the third and fifth insulator materials; and
- each of the third and fourth insulator materials having greater k than each of the fifth and sixth insulator materials.
39. The structure of claim 38 wherein,
- each of the third and fourth insulator materials has K greater than 4.0; and
- each of the fifth and sixth insulator materials has K no greater than 4.0.
40. The structure of claim 39 wherein the first insulator material has k no greater than 4.0.
Type: Application
Filed: Mar 20, 2018
Publication Date: Nov 8, 2018
Applicant: Micron Technology, Inc. (Boise, ID)
Inventors: Sourabh Dhir (Boise, ID), Andrew L. Li (Boise, ID), Sanh D. Tang (Kuna, ID), Naoyoshi Kobayashi (Tokyo), Katsumi Koge (Tokyo)
Application Number: 15/926,505