Patents by Inventor Sreenath Kurupati

Sreenath Kurupati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100165206
    Abstract: In some embodiments, a method of processing a video sequence may include receiving an input video sequence having an input video sequence resolution, aligning images from the input video sequence, reducing noise in the aligned images, and producing an output video sequence from the reduced noise images, wherein the output video sequence has the same resolution as the input video sequence resolution. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Inventors: Oscar Nestares, Horst W. Haussecker, Scott M. Ettinger, Yoram Gat, Sreenath Kurupati
  • Publication number: 20100156934
    Abstract: A video display controller may be implemented by a plurality of identical hardware blend stages that can be coupled together to produce the desired blend of video, graphics, overlays, and the like. Each of the various video planes to be blended can be multiplied by an alpha value to selectively apply alpha values to particular video planes. At least two video display windows may be selectively produced by the coupled blend stages.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Inventors: Wujian Zhang, Alok Mathur, Sreenath Kurupati, Dmitrii Loukianov, Peter Munguia
  • Publication number: 20100079497
    Abstract: A video scaler is disclosed. A polyphase filter can be used to generate interpolated pixels. The values of pixels adjacent an interpolated pixel are examined to determine variation in values among the adjacent pixels to determine minimum and maximum value variations. The value of the interpolated pixel is limited based on the minimum and maximum value variations. Ringing artifacts can be reduced by limiting the color range of an interpolated pixel.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 1, 2010
    Inventor: Sreenath Kurupati
  • Publication number: 20100073386
    Abstract: A computer system may comprise a graphics controller, which may support a display handler. In one embodiment, the display handler may receive configuration values comprising a quantity value and a blending order. In one embodiment, the display handler may determine the number of universal pixel planes using the quantity value. The display handler may provide a number of universal pixel planes equal to the quantity value and the universal pixel planes may be provided using a reference universal pixel plane. The display handler may render each of the universal pixel planes into a type of pixel plane indicated by the corresponding elements of the blending order.
    Type: Application
    Filed: September 23, 2008
    Publication date: March 25, 2010
    Inventors: Wujian Zhang, Alok Mathur, Sreenath Kurupati
  • Patent number: 7542053
    Abstract: A method includes receiving a sequence of samples that represents a row of pixels in an image. The method further includes selecting a re-scaling factor for at least a portion of the row of pixels. The method further includes selecting a filter from a bank of low pass filters based on the selected re-scaling factor, and low-pass filtering the sequence of samples with the selected filter. The method further includes up-sampling the low-pass-filtered sequence of samples by a factor M with a polyphase filter bank having a windowed sinc(t) characteristic to the up-sampled sequence of samples, and down-sampling the polyphase-filtered sequence of samples.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: June 2, 2009
    Assignee: Intel Corporation
    Inventors: Inaki Berenguer, Raju Hormis, Sreenath Kurupati
  • Patent number: 7542535
    Abstract: A method includes receiving a serial data signal including a preamble and an embedded clock signal having an embedded clock signal frequency, and processing the preamble using logic to determine the embedded clock signal frequency. An apparatus includes a counter unit, a state machine, and a logic unit. The counter unit includes a data port, a clock port and a plurality of counters. In operation, the data port receives a serial data signal and the clock port receives a clock signal having a clock signal frequency. The serial data signal includes a preamble and an embedded clock signal having an embedded clock signal frequency. The state machine identifies at least one of the plurality of counters to count between transitions in the preamble in response to the clock signal. The logic unit is coupled to the plurality of counters and determines the embedded clock signal frequency.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: June 2, 2009
    Assignee: Intel Corporation
    Inventor: Sreenath Kurupati
  • Patent number: 7516126
    Abstract: A method and apparatus to perform a multi-field matching search. A search unit groups single fields of a multiple-field source into a search target having multiple-field keys (MFKs) whose single fields correspond to the single fields in multiple-field vectors (MFVs) of entries in a data structure. The search unit generates a set of queries based, at least in part, on the MFKs, where each query has a different MFK as a lead MFK. The search unit determines, based, at least in part, on a query, whether the non-wildcard values in the MFVs of an entry match the non-wildcard values in corresponding MFKs of the search target.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Miguel Guerrero, Kinyip Sit, Sreenath Kurupati
  • Patent number: 7515766
    Abstract: A method and apparatus for hardware-base edge handling in video post-processing. In one embodiment, the method includes the identification of at least one unstored input pixel required to compute an output pixel during output pixel computation. Once identified, a pixel value is generated for the at least one unstored input pixel according to a detected edge handling mode. The generation of the pixel value for the unstored input pixel is performed, in one embodiment, if a position of the unstored input pixel is outside a pixel frame boundary. For example, in one embodiment, for output pixel computation of a scaling operation, the frame boundaries include a left (top) edge and a right (bottom) edge for which input pixels required to compute output pixels at or near the frame boundaries do not exist. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Sreenath Kurupati, Brian R. Nickerson, Samuel Wong, Sunil Chaudhari, Jonathan W. Liu
  • Patent number: 7467151
    Abstract: A data structure for use in database applications. The data structure includes a key database that is searchable via an index table.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: December 16, 2008
    Assignee: Intel Corporation
    Inventors: Sreenath Kurupati, Miguel A. Guerrero
  • Patent number: 7446820
    Abstract: A method includes receiving a sequence of input samples that represents a row of pixels in an image. The method further includes selecting a re-scaling factor for at least a portion of the row of pixels. The method further includes determining a phase offset based on the selected re-scaling factor, and applying a direct B-spline transform to a group of the samples to generate transform coefficients. The method further includes providing the transform coefficients as an input to a filter bank, and applying the phase offset at an output of the filter bank to generate a sequence of output samples.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: November 4, 2008
    Assignee: Intel Corporation
    Inventors: Kuo-Ching Liang, Raju Hormis, Sreenath Kurupati
  • Publication number: 20080049037
    Abstract: Apparatus, systems and methods for display processing line buffers incorporating pipeline overlap are disclosed. For example, an apparatus is disclosed including processing logic to use pixel processing algorithms to process a pixel value of a first portion of an image, and line buffers coupled to the processing logic. The line buffers to hold at least some pixel values of other portions of the image adjacent to the first portion. Where the pixel values of the other portions of the image held by the line buffers correspond to pixel values of the adjacent portions of the image that are to be convolved by the pixel processing algorithms with the pixel value of the first portion. Other implementations are also disclosed.
    Type: Application
    Filed: August 25, 2006
    Publication date: February 28, 2008
    Inventor: Sreenath Kurupati
  • Patent number: 7236499
    Abstract: According to some embodiments, a resource is allocated in accordance with a masked request vector. For example, a masking unit may receive a request vector and provide a masked request vector, wherein each bit in the request vector represents a requestor and indicates if that requestor is requesting a resource. A first priority encoder may receive the masked request vector from the masking unit and output a signal indicating a selected requestor. According to some embodiments, a second priority encoder may receive the un-masked request vector and output a signal indicating an alternate selected requestor.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventor: Sreenath Kurupati
  • Patent number: 7236497
    Abstract: According to some embodiments, a requester is selected in accordance with information associated with a first and second groups of requesters. For example, a first input may receive a first priority signal, indicating whether at least one of a first group of requesters is requesting to be selected, along with a first identifier that may indicate a particular one of the first group of requesters. Similarly, a second input may a second priority signal, indicating whether at least one of a second group of requesters is requesting to be selected, along with a second identifier that may indicate a particular one of the second group of requesters. An output might then provide the first identifier if the first priority signal indicates that at least one of the first group of requesters is requesting to be selected.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventor: Sreenath Kurupati
  • Patent number: 7161908
    Abstract: According to some embodiments, spare processing cycles are inserted into a stream of information packets to facilitate operation of a control unit.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: January 9, 2007
    Assignee: Intel Corporation
    Inventor: Sreenath Kurupati
  • Publication number: 20060227152
    Abstract: A method includes receiving a sequence of samples that represents a row of pixels in an image. The method further includes selecting a re-scaling factor for at least a portion of the row of pixels. The method further includes selecting a filter from a bank of low pass filters based on the selected re-scaling factor, and low-pass filtering the sequence of samples with the selected filter. The method further includes up-sampling the low-pass-filtered sequence of samples by a factor M with a polyphase filter bank having a windowed sinc(t) characteristic to the up-sampled sequence of samples, and down-sampling the polyphase-filtered sequence of samples.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 12, 2006
    Inventors: Inaki Berenguer, Raju Hormis, Sreenath Kurupati
  • Publication number: 20060221245
    Abstract: A method includes receiving a sequence of input samples that represents a row of pixels in an image. The method further includes selecting a re-scaling factor for at least a portion of the row of pixels. The method further includes determining a phase offset based on the selected re-scaling factor, and applying a direct B-spline transform to a group of the samples to generate transform coefficients. The method further includes providing the transform coefficients as an input to a filter bank, and applying the phase offset at an output of the filter bank to generate a sequence of output samples.
    Type: Application
    Filed: March 30, 2005
    Publication date: October 5, 2006
    Inventors: Kuo-Ching Liang, Raju Hormis, Sreenath Kurupati
  • Patent number: 7111093
    Abstract: According to some embodiments, a ping-pong buffer system has a buffer that stores a subset of data from a data source.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: September 19, 2006
    Assignee: Intel Corporation
    Inventors: Muraleedhara Navada, Sreenath Kurupati
  • Publication number: 20060122989
    Abstract: A data structure for use in database applications. The data structure includes a key database that is searchable via an index table.
    Type: Application
    Filed: January 25, 2006
    Publication date: June 8, 2006
    Inventors: Sreenath Kurupati, Miguel Guerrero
  • Patent number: 7058642
    Abstract: Method and data structure for a low memory overhead database and apparatus for implementing the same. Under one embodiment, the data structure includes an index table for storing a plurality of entries, each of the entries corresponding to one of a plurality of hash values, with each entry including a section pointer to identify a memory address of one of a plurality of sections of a key database and including valid bits to indicate a size of the respective section of the key database. The key database is stores a plurality of data entries, with each data entry including a search key having one of the plurality of hash values, and wherein the data entries are grouped into the plurality of sections, with each section storing data entries with search keys having the same hash value.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Sreenath Kurupati, Miguel A. Guerrero
  • Publication number: 20060092320
    Abstract: A portion of a video frame is transferred via a memory burst transfer, from memory to an on-chip buffer. The on-chip buffer has a width that is the same as the memory burst width for the memory. Video processing is performed upon the transferred portion. Other embodiments are also described and claimed.
    Type: Application
    Filed: October 29, 2004
    Publication date: May 4, 2006
    Inventors: Brian Nickerson, Samuel Wong, Sunil Chaudhari, Jonathan Liu, Sreenath Kurupati