Abstract: A method and apparatus for hardware-based anamorphic video scaling. In one embodiment, the method includes the fetch of zero or more new input pixels according to an entry of an input control memory corresponding to a current output pixel. Once fetched, the zero or more new input pixels replace at least one stored input pixel of N, input pixels. Using the updated N, input pixels and an N, coefficient set selected according to an entry of a coefficient memory corresponding to the current output pixel, a pixel computation, such as, for example, an anamorphic scaling computation, is performed. In one embodiment, the anamorphic scaling is performed by subdividing an X×Y pixel frame into X/M M×Y pixel subframes. Other embodiments are described and claimed.

Abstract: A method and apparatus for hardware-base edge handling in video post-processing. In one embodiment, the method includes the identification of at least one unstored input pixel required to compute an output pixel during output pixel computation. Once identified, a pixel value is generated for the at least one unstored input pixel according to a detected edge handling mode. The generation of the pixel value for the unstored input pixel is performed, in one embodiment, if a position of the unstored input pixel is outside a pixel frame boundary. For example, in one embodiment, for output pixel computation of a scaling operation, the frame boundaries include a left (top) edge and a right (bottom) edge for which input pixels required to compute output pixels at or near the frame boundaries do not exist. Other embodiments are described and claimed.

Abstract: An apparatus and a system, as well as a method and article, may operate to interchangeably store audio data associated with an audio interface protocol selected from a plurality of audio interface protocols in a polymorphic memory structure capable of being coupled to a common digital input-output interface.

Abstract: A method includes receiving a serial data signal including a preamble and an embedded clock signal having an embedded clock signal frequency, and processing the preamble using logic to determine the embedded clock signal frequency. An apparatus includes a counter unit, a state machine, and a logic unit. The counter unit includes a data port, a clock port and a plurality of counters. In operation, the data port receives a serial data signal and the clock port receives a clock signal having a clock signal frequency. The serial data signal includes a preamble and an embedded clock signal having an embedded clock signal frequency. The state machine identifies at least one of the plurality of counters to count between transitions in the preamble in response to the clock signal. The logic unit is coupled to the plurality of counters and determines the embedded clock signal frequency.

Abstract: A method and system for performing inserts and lookups in fully associative sections of memory is provided. The system includes a differentiating register to store information that differentiates entries in a section of a memory, logic coupled to the register to determine which entry is most likely to match a search key, and a comparator to compare the search key to the entry determined most likely to match. For each pair of entries in the section of memory, a differentiating bit position, reference value, and pointer are determined and stored to differentiate the entries. A search key can be compared to the differentiating values to determine which entry is most likely to match. Then, the entry determined most likely to match is retrieved from memory and compared to the search key.

Abstract: A method and apparatus to perform a multi-field matching search. A search unit groups single fields of a multiple-field source into a search target having multiple-field keys (MFKs) whose single fields correspond to the single fields in multiple-field vectors (MFVs) of entries in a data structure. The search unit generates a set of queries based, at least in part, on the MFKs, where each query has a different MFK as a lead MFK. The search unit determines, based, at least in part, on a query, whether the non-wildcard values in the MFVs of an entry match the non-wildcard values in corresponding MFKs of the search target.

Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

Abstract: A technique for decreasing VLAN lookup times in hardware-based packet switches by emulating the functionality of a content addressable memory (CAM) with software and random access memories (RAM). The decrease in lookup time is achieved by using content from the data packet to index directly into a table that stores forwarding information. Since the forwarding information is addressed directly by content from the packet, the need to spend time and resources sorting through the table of forwarding information with a key search is eliminated.

Abstract: According to some embodiments, a ping-pong buffer system has a buffer that stores a subset of data from a data source.

Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

Abstract: A method and system for maximizing DRAM memory bandwidth is provided. The system includes a plurality of buffers to store a plurality of data units, a selector coupled to the buffers to select the buffer to which a data unit is to be stored, and logic coupled to the buffers to schedule an access of one of a corresponding number of memory banks based on the buffer in which the data unit is stored. The system receives a data unit, computes an index based on at least a portion of the data unit, selects a buffer in which to store the data unit based on the index, stores the data unit in the selected buffer, schedules a memory bank access based on the index, reads the data unit from the selected buffer, and accesses the memory bank.

Abstract: According to some embodiments, spare processing cycles are inserted into a stream of information packets to facilitate operation of a control unit.

Abstract: According to some embodiments, a memory structure is provided including information storage elements and associated validity storage elements.

Abstract: According to some embodiments, a requester is selected in accordance with information associated with a first and second groups of requesters.

Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.

Abstract: A method and system for performing inserts and lookups in fully associative sections of memory is provided. The system includes a differentiating register to store information that differentiates entries in a section of a memory, logic coupled to the register to determine which entry is most likely to match a search key, and a comparator to compare the search key to the entry determined most likely to match. For each pair of entries in the section of memory, a differentiating bit position, reference value, and pointer are determined and stored to differentiate the entries. A search key can be compared to the differentiating values to determine which entry is most likely to match. Then, the entry determined most likely to match is retrieved from memory and compared to the search key.

Abstract: Described herein is a method and apparatus for memory efficient fast VLAN lookups and inserts in hardware-based packet switches.

Abstract: A method and system for maximizing DRAM memory bandwidth is provided. The system includes a plurality of buffers to store a plurality of data units, a selector coupled to the buffers to select the buffer to which a data unit is to be stored, and logic coupled to the buffers to schedule an access of one of a corresponding number of memory banks based on the buffer in which the data unit is stored. The system receives a data unit, computes an index based on at least a portion of the data unit, selects a buffer in which to store the data unit based on the index, stores the data unit in the selected buffer, schedules a memory bank access based on the index, reads the data unit from the selected buffer, and accesses the memory bank.

Abstract: A data structure for use in database applications. The data structure includes a key database that is searchable via an index table.

Abstract: A method for ordering input variables in binary decision diagrams is described. Once a plurality of disjoint sets of input variables can be found from the sub-equations of a Boolean function, an initial top-level order can be used to form a significantly smaller diagram. The diagram can by reduced further by application of the method recursively on the sub-equations and successive sub-equations until primary inputs are reached.