Patents by Inventor Sreenath Kurupati

Sreenath Kurupati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Performance verification/analysis tool for full-chip designs
    Patent number: 6564357
    Abstract: A method and apparatus may be provided for providing performance verification/analysis of a full-chip design. This may include performing an analysis on a first block of the full-chip design. Data (such as a waveform output from a pin of the block) may be captured while performing the analysis. This captured data may be utilized when performing an analysis of the full-chip design. Features of an interconnect between the first block and a second block may be determined using the captured data.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: May 13, 2003
    Assignee: Intel Corporation
    Inventors: Rony Kay, Sreenath Kurupati
  • Ordering binary decision diagrams used in the formal equivalence verification of digital designs
    Publication number: 20030023942
    Abstract: A method for ordering input variables in binary decision diagrams is described. Once a plurality of disjoint sets of input variables can be found from the sub-equations of a Boolean function, an initial top-level order can be used to form a significantly smaller diagram. The diagram can by reduced further by application of the method recursively on the sub-equations and successive sub-equations until primary inputs are reached.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 30, 2003
    Inventor: Sreenath Kurupati
  • Performance verification/analysis tool for full-chip designs
    Publication number: 20020144225
    Abstract: A method and apparatus may be provided for providing performance verification/analysis of a full-chip design. This may include performing an analysis on a first block of the full-chip design. Data (such as a waveform output from a pin of the block) may be captured while performing the analysis. This captured data may be utilized when performing an analysis of the full-chip design. Features of an interconnect between the first block and a second block may be determined using the captured data.
    Type: Application
    Filed: March 30, 2001
    Publication date: October 3, 2002
    Inventors: Rony Kay, Sreenath Kurupati