Abstract: A processor and method are described for a multi-level reservation station.

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

Abstract: An apparatus and method for performing efficient, adaptable tensor operations.

Abstract: Disclosed are synthetic diamond materials for quantum and optical applications, such as quantum information processing, quantum key distribution, quantum repeaters, and quantum sensing devices, based on spin defects in diamond. This includes methods for synthesizing and treating diamond in order to create spin defects with improved spin coherence and optical emission properties, as well as treating the diamond to eliminate unwanted defects that degrade these properties.

Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

Abstract: In general, embodiments of the invention relate to a method and system for managing persistent storage in a local computing device. More specifically, embodiments of the invention relate to determining the amount of space that will be freed up (or become available) in the persistent storage during a data transfer using a perfect hash function. Once the amount of data to be transferred is determined, embodiments of the invention initiate the allocation of an appropriate amount of space in the remote storage device and, subsequently, initiate the transfer of the data to the remote storage device.

Abstract: An apparatus and method for offloading iterative, parallel work to a data parallel cluster. For example, one embodiment of a processor comprises: a host processor to execute a primary thread; a data parallel cluster coupled to the host processor over a high speed interconnect, the data parallel cluster comprising a plurality of execution lanes to perform parallel execution of one or more secondary threads related to the primary thread; and a data parallel cluster controller integral to the host processor to offload processing of the one or more secondary threads to the data parallel cluster in response to one of the cores executing a parallel processing call instruction from the primary thread.

Abstract: A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

Abstract: A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

Abstract: A wide-voltage range, failsafe output interface module including a low-voltage, drain extended MOSFETs has been proposed to prevent the flow of reverse current during a failsafe operation while ensuring the MOSFETs are not subject to voltage over their voltage tolerance levels, improving reliability of an output interface module without resorting to more costly transistors with thicker films.

Abstract: In an embodiment, a method for validating data integrity of a seeding process is described. The seeding process for migrating data from a source tier to a target tier persists a perfect hash vector (PHV) to a disk when the seeding process is suspended for various reasons. The PHV includes bits for fingerprints for data segments corresponding to the data, and can be reloaded into memory upon resumption of the seeding process. One or more bits corresponding to fingerprints for copied data segments are reset prior to starting the copy phase in the resumed run. A checksum of the PHV is calculated after the seeding process completes copying data segments in the containers. A non-zero checksum of the PHV indicates that one or more data segments are missing on the source tier or the data segments are not successfully copied to the target tier. The missing data segments and/or one or more related files are reported to a user via a user interface.

Abstract: A wide-voltage range, failsafe output interface module including a low-voltage, drain extended MOSFETs has been proposed to prevent the flow of reverse current during a failsafe operation while ensuring the MOSFETs are not subject to voltage over their voltage tolerance levels, improving reliability of an output interface module without resorting to more costly transistors with thicker films.

Abstract: In an embodiment, a method for validating data integrity of a seeding process is described. The seeding process for migrating data from a source tier to a target tier persists a perfect hash vector (PHV) to a disk when the seeding process is suspended for various reasons. The PHV includes bits for fingerprints for data segments corresponding to the data, and can be reloaded into memory upon resumption of the seeding process. One or more bits corresponding to fingerprints for copied data segments are reset prior to starting the copy phase in the resumed run. A checksum of the PHV is calculated after the seeding process completes copying data segments in the containers. A non-zero checksum of the PHV indicates that one or more data segments are missing on the source tier or the data segments are not successfully copied to the target tier. The missing data segments and/or one or more related files are reported to a user via a user interface.

Abstract: In an embodiment, a system and method for supporting a seeding process with suspend and resume capabilities are described. A resumable seeding component in a data seeding module can be used to move data from a source tier to a target tier. A resumption context including a perfect hash function (PHF) and a perfect hash vector (PHV) persists a state of a seeding process at the end of each operation in the seeding process. The PHV represents data segments of the data using the PHF. The resumption context is loaded into memory upon resumption of the seeding process after it is suspended. Information in the resumable context is used to determine a last successfully completed operation, and a last copied container. The seeding process is resumed by executing an operation following the completed operation in the resumable context.

Abstract: In general, embodiments of the invention relate to a method and system for managing persistent storage in a local computing device. More specifically, embodiments of the invention relate to determining the amount of space that will be freed up (or become available) in the persistent storage during a data transfer using a perfect hash function. Once the amount of data to be transferred is determined, embodiments of the invention initiate the allocation of an appropriate amount of space in the remote storage device and, subsequently, initiate the transfer of the data to the remote storage device.

Abstract: An Inter-IC interface with a glitch filter including at least two cascaded RC filters configured to compensate a signal skew of the data or clock signal received from a data communication or clock signal line, feedback switches configured to pull up or pull down a voltage at an output node of each of the at least two cascaded RC filters, and feedforward transistors configured to condition a respective switches to the feedback switches to accelerate the pull up or the pull down.

Abstract: An apparatus and method for data parallel single program multiple data (SPMD) execution. For example, one embodiment of a processor comprises: instruction fetch circuitry to fetch instructions of one or more primary threads; a decoder to decode the instructions to generate uops; a data parallel cluster (DPC) to execute microthreads comprising a subset of the uops, the DPC further comprising: a plurality of execution lanes to perform parallel execution of the microthreads; an instruction decode queue (IDQ) to store the uops prior to execution; and a scheduler to evaluate the microthreads based on associated variables including instruction pointer (IP) values, the scheduler to gang microthreads into fragments for parallel execution on the execution lanes based on the evaluation.

Abstract: An apparatus and method for performing efficient, adaptable tensor operations.

Abstract: Aspects of the present disclosure provide for a circuit. In at least some examples, the circuit includes a first diode, a second diode, a comparator having a comparator first arm and a comparator second arm, and an inverter. The first diode has a first terminal coupled to a first node and a second terminal. The second diode is coupled in series between the second terminal of the first diode and a second node. The comparator first arm includes a first plurality of transistor devices and is coupled to a third node. The comparator second arm includes a second plurality of transistor devices and is coupled to the second node, wherein the second plurality of transistor devices is greater in number than the first plurality of transistor devices. The inverter has an input coupled to the comparator and an output coupled to a fourth node.

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.