Patents by Inventor Srinivas Gandikota

Srinivas Gandikota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240222195
    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the present disclosure advantageously provide methods of manufacturing electronic devices which meet reduced thickness, lower thermal budget, and Vt requirements, and have improved device performance and reliability. Advantageously, the embodiments of the present disclosure provide methods of manufacturing electronic devices that achieve desired dipole effect without an annealing process. To achieve desired dipole effect that is “thinner” than 3 ?, embodiments of the disclosure advantageously include methods of controlling surface adsorption equilibrium and, in turn, controlling the fraction of substrate surface atomic sites that are occupied by dipole species, which is not considered to be achievable by ALD processes.
    Type: Application
    Filed: February 13, 2023
    Publication date: July 4, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Tianyi Huang, Srinivas Gandikota, Yixiong Yang, Tengzhou Ma, Steven C.H. Hung, Hsin-Jung Yu, Geetika Bajaj
  • Publication number: 20240218502
    Abstract: Embodiments of the disclosure are directed to methods of depositing a molybdenum film directly on a substrate surface (e.g., a low-? dielectric material) by exposing the substrate surface to a molybdenum-containing precursor and an organosilane reducing agent at a temperature of less than or equal to 450° C. The molybdenum-containing precursor comprises one or more of molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), molybdenum hexafluoride (MoF6), molybdenum hexacarbonyl, bis(tert-butylimido)-bis(dimethylamido)molybdenum, or bis(ethylbenzene) molybdenum. The organosilane reducing agent comprises trimethylsilyl compounds, such as 1,4-bis(trimethylsilyl)-2-methyl-2,5-cyclohexadiene.
    Type: Application
    Filed: January 4, 2023
    Publication date: July 4, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Tuerxun Ailihumaer, Srinivas Gandikota, Yixiong Yang, Yogesh Sharma, Ashutosh Agarwal, Mandyam Sriram
  • Patent number: 12020982
    Abstract: A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: June 25, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Steven C. H. Hung, Srinivas D. Nemani, Yixiong Yang, Susmit Singha Roy, Nikolaos Bekiaris
  • Patent number: 12022650
    Abstract: Methods for DRAM device with a buried word line are described. The method includes forming a metal cap layer and a molybdenum conductor layer in a feature on a substrate. The method includes depositing the metal cap layer on the substrate by physical vapor deposition (PVD) and depositing the molybdenum conductor layer by atomic layer deposition (ALD) on the metal cap layer.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: June 25, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yixiong Yang, Jacqueline S. Wrench, Yong Yang, Srinivas Gandikota, Annamalai Lakshmanan, Joung Joo Lee, Feihu Wang, Seshadri Ganguli
  • Publication number: 20240204061
    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide methods to reduce the resistance of the work function layer of an electronic device, as well as using a low resistivity metal for filling the gate.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 20, 2024
    Inventors: Srinivas Gandikota, Yixiong Yang, Yongjing Lin, Tuerxun Ailihumaer, Tengzhou Ma, Yuanhua Zheng, Zhihui Liu, Shih Chung Chen, Janardhan Devrajan, Yi Xu, Yu Lei, Mandyam Sriram
  • Publication number: 20240194526
    Abstract: A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.
    Type: Application
    Filed: February 20, 2024
    Publication date: June 13, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Steven C.H. Hung, Srinivas D. Nemani, Yixiong Yang, Susmit Singha Roy, Nikolaos Bekiaris
  • Publication number: 20240183033
    Abstract: Embodiments of the present disclosure advantageously provide improved control over precursor/reactant pulse/purge time, greater growth per cycle, and higher throughput during formation of a metal-containing film on a substrate surface (including substrate surfaces having at least one feature) compared to traditional atomic layer deposition (ALD) processes. In some embodiments, forming the metal-containing film comprises exposing a substrate to a constant flow of an inert carrier gas and a co-flow of a pulse of a metal-containing precursor and a pulse of a reactant. The pulse of the metal-containing precursor and the pulse of the reactant may be interrupted by a mini purge. The metal-containing precursor and/or the reactant may be charged during the mini purge to avoid precursor/reactant depletion.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Tianyi Huang, Srinivas Gandikota, Yixiong Yang, Elizabeth Mao, Chi-Chou Lin
  • Patent number: 11996455
    Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: May 28, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yongjing Lin, Karla M Bernal Ramos, Shih Chung Chen, Yixiong Yang, Lin Dong, Steven C. H. Hung, Srinivas Gandikota
  • Patent number: 11997849
    Abstract: A memory device comprises: a stack of alternating silicon oxide layers and wordline layers; each of the wordline layers comprising dipole regions adjacent to the silicon oxide layers, the dipole regions comprising a nitride, a carbide, an oxide, a carbonitride, or combinations thereof of a dipole metal. The dipole regions are formed by driving a dipole film into a gate oxide layer of the wordline layers, and any residual dipole film is removed.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: May 28, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Yong Yang, Jacqueline S. Wrench, Yixiong Yang, Pradeep K. Subrahmanyan, Srinivas Gandikota
  • Publication number: 20240170254
    Abstract: Embodiments of the disclosure are directed to PEALD batch processing chambers. Some embodiments are directed to processing chambers having one or more inductively coupled plasma (ICP) coils electrically connected to at least one RF power source. Some embodiments are directed to processing chambers having a wafer cassette comprising a plurality of platforms, each platform configured to support at least one wafer for processing, and one or more RF power sources electrically connected to the plurality of platforms in the wafer cassette. In some embodiments, the plurality of platforms have a first set of electrodes having a first polarity and a second set of electrodes having a second polarity, and one or more RF power sources electrically connected to the plurality of platforms in the wafer cassette.
    Type: Application
    Filed: November 21, 2022
    Publication date: May 23, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Jianming Fu, Tza-Jing Gung, Sanjeev Baluja, Haitao Wang, Mandyam Sriram, Srinivas Gandikota, Steven V. Sansoni
  • Publication number: 20240154018
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Ria Someshwar, Seshadri Ganguli, Lan Yu, Siddarth Krishnan, Srinivas Gandikota, Jacqueline S. Wrench, Yixiong Yang
  • Patent number: 11961734
    Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: April 16, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Yixiong Yang, Jacqueline Samantha Wrench, Yong Yang, Steven C. H. Hung
  • Patent number: 11955332
    Abstract: A method of forming a high-? dielectric cap layer on a semiconductor structure formed on a substrate includes depositing the high-? dielectric cap layer on the semiconductor structure, depositing a sacrificial silicon cap layer on the high-? dielectric cap layer, performing a post cap anneal process to harden and densify the as-deposited high-? dielectric cap layer, and removing the sacrificial silicon cap layer.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 9, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Srinivas Gandikota, Yixiong Yang, Jacqueline Samantha Wrench, Yong Yang, Steven C. H. Hung
  • Publication number: 20240102157
    Abstract: Embodiments of the disclosure are directed to methods of depositing a molybdenum film directly on a substrate surface (e.g., a low-K dielectric material) by exposing the substrate surface to a molybdenum-containing precursor and a plasma at a temperature of less than or equal to 400° C. The molybdenum-containing precursor comprises one or more of molybdenum pentachloride (MoCl5), molybdenum dioxide dichloride (MoO2Cl2), molybdenum oxytetrachloride (MoOCl4), molybdenum hexacarbonyl, bis(tert-butylimido)-bis(dimethylamido)molybdenum, or bis(ethylbenzene) molybdenum. The plasma comprises one or more of hydrogen (H2), nitrogen (N2), or a silane (SixHy). In some embodiments, when the molybdenum-containing precursor comprises molybdenum hexafluoride (MoF6), the plasma does not include hydrogen (H2).
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Applicant: Applied Materials, Inc.
    Inventors: TUERXUN AILIHUMAER, Srinivas Gandikota, Yixiong Yang, Yogesh Sharma, Ashutosh Agarwal, Mandyam Sriram
  • Patent number: 11932939
    Abstract: Apparatus for processing a substrate are provided herein. In some embodiments, a lid for a substrate processing chamber includes: a lid plate comprising an upper surface and a contoured bottom surface, the upper surface having a central opening and the contoured bottom surface having a first portion that extends downwardly and outwardly from the central opening to a peripheral portion of the lid plate and a second portion that extends radially outward along the peripheral portion of the lid plate; an upper flange extending radially outward from the lid plate; and one or more channels formed through the lid plate from the upper surface of the lid plate to the second portion of the contoured bottom surface.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 19, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Muhammad M. Rasheed, Srinivas Gandikota, Mario Dan Sanchez, Guoqiang Jian, Yixiong Yang, Deepak Jadhav, Ashutosh Agarwal
  • Publication number: 20240087899
    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. The methods include treating a surface of a metal gate stack with a radical treatment. The radical treatment may be used to treat one or more layers or surfaces of layers in the metal gate stack. The radical treatment may be performed once or multiple times during the methods described herein. The radical treatment comprises flowing one or more of nitrogen radicals (N2*) and hydrogen radicals (H*) over the surface of the metal gate stack.
    Type: Application
    Filed: September 9, 2022
    Publication date: March 14, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Zhihui Liu, Seshadri Ganguli, Tianyi Huang, Yixiong Yang, Srinivas Gandikota, Yuanhua Zheng, Yongjing Lin, Keyur Karandikar, Elizabeth Mao
  • Publication number: 20240060175
    Abstract: Embodiments of the disclosure provide conformally deposited molybdenum films having reduced resistivity and methods of forming the same. The methods include forming a nucleation layer directly on a dielectric layer on a substrate surface by exposing the substrate surface to a molybdenum-containing precursor and a nucleation reactant, and conformally depositing a molybdenum film on the nucleation layer. Another aspect of the disclosure pertains to a method that is part of a gap fill process, comprising forming a nucleation layer directly on a dielectric region within one or more high aspect ratio gap features, including vertical gap features and/or horizontal gap features, and conformally depositing a molybdenum film on the nucleation layer to fill the feature.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Yixiong Yang, Yong Yang, Tuerxun Ailihumaer, Yogesh Sharma, Kunal Bhatnagar, Mohith Verghese
  • Publication number: 20240063064
    Abstract: Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide electronic devices which comprise a dipole region and meet reduced thickness and lower thermal budget requirements. The electronic devices described herein comprise a source region, a drain region, and a channel separating the source region and the drain region, an interfacial layer on a top surface of the channel, a high-? dielectric layer on the interfacial layer, a dipole layer on the high-? dielectric layer, and optionally, a capping layer on the dipole layer. In some embodiments, the methods comprise annealing the substrate to drive atoms from the dipole layer into one or more of the interfacial layer or the high-? dielectric layer.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Yixiong Yang, Tianyi Huang, Tengzhou Ma, Seshadri Ganguli
  • Patent number: 11908914
    Abstract: Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: February 20, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Ria Someshwar, Seshadri Ganguli, Lan Yu, Siddarth Krishnan, Srinivas Gandikota, Jacqueline S. Wrench, Yixiong Yang
  • Patent number: 11887856
    Abstract: Methods of depositing a film by atomic layer deposition are described. The methods comprise exposing a substrate surface to a first process condition comprising a first reactive gas and a second reactive gas and exposing the substrate surface to a second process condition comprising the second reactive gas. The first process condition comprises less than a full amount of the second reactive gas for a CVD process.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: January 30, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kelvin Chan, Yihong Chen, Jared Ahmad Lee, Kevin Griffin, Srinivas Gandikota, Joseph Yudovsky, Mandyam Sriram