Patents by Inventor Srinivas Kumar

Srinivas Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240004677
    Abstract: Generally, the present disclosure is directed to user interface understanding. More particularly, the present disclosure relates to training and utilization of machine-learned models for user interface prediction and/or generation. A machine-learned interface prediction model can be pre-trained using a variety of pre-training tasks for eventual downstream task training and utilization (e.g., interface prediction, interface generation, etc.).
    Type: Application
    Filed: September 13, 2023
    Publication date: January 4, 2024
    Inventors: Srinivas Kumar Sunkara, Xiaoxue Zang, Ying Xu, Lijuan Liu, Nevan Holt Wichers, Gabriel Overholt Schubiner, Jindong Chen, Abhinav Kumar Rastogi, Blaise Aguera-Arcas, Zecheng He
  • Publication number: 20230412186
    Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Nagarajan VISWANATHAN, Himanshu VARSHNEY, Vinam ARORA, Charls BABU, Srinivas Kumar NARU
  • Patent number: 11818108
    Abstract: A trust chain having client system and a remote system in a secure connection, wherein an intermediary system associated with the network flow path serves as a signing entity to establish an end to end transitive trust. The intermediate system is a corroborative entity in the operations technology realm of the client system. The remote system serves as the host for a plurality of services in the information technology realm. A two way handshake during the initial secure exchange protocol between a local client application and a remote service is extended to a three way handshake that includes a nonce issued by the remote service on the remote system and a digital signature for the nonce issued by a signature service on an associated intermediate system. The nonce signature is verified authoritatively at the remote system based on the signing certificate of the intermediate system for explicit proof of association.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: November 14, 2023
    Assignee: DigiCert, Inc.
    Inventors: Srinivas Kumar, Shashank Jaywant Pandhare, Atul Gupta, Gopal Raman
  • Patent number: 11789753
    Abstract: Generally, the present disclosure is directed to user interface understanding. More particularly, the present disclosure relates to training and utilization of machine-learned models for user interface prediction and/or generation. A machine-learned interface prediction model can be pre-trained using a variety of pre-training tasks for eventual downstream task training and utilization (e.g., interface prediction, interface generation, etc.).
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: October 17, 2023
    Assignee: GOOGLE LLC
    Inventors: Srinivas Kumar Sunkara, Xiaoxue Zang, Ying Xu, Lijuan Liu, Nevan Holt Wichers, Gabriel Overholt Schubiner, Jindong Chen, Abhinav Kumar Rastogi, Blaise Aguera-Arcas, Zecheng He
  • Patent number: 11784660
    Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: October 10, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nagarajan Viswanathan, Himanshu Varshney, Vinam Arora, Charls Babu, Srinivas Kumar Naru
  • Patent number: 11755583
    Abstract: A system, method, and computer-readable medium for proving feedback on database instructions, identifying, for example, existing patterns and providing suggested replacement instructions. This may have the effect of improving the efficiency of instructions used to create and/or manipulate databases. According to some aspects, these and other benefits may be achieved by parsing received instructions into an organizational structure, traversing the organizational structure for known patterns, and suggesting replacement patterns. In implementation, this may be effected by receiving one or more sets of known patterns and corresponding replacement patterns, parsing received instructions, comparing the known patterns with the parsed instructions, and providing suggested replacement patterns based on one or more known patterns matching the parsed instructions. A benefit of may include reducing Cartesian products during the merging of tables.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: September 12, 2023
    Assignee: Capital One Services, LLC
    Inventors: Dennis J. Mire, Puneet Goyal, Siddharth Gupta, Srinivas Kumar, Deepak Sundararaj, Oron Hazi
  • Publication number: 20230275082
    Abstract: In an example, a device includes a semiconductor substrate having a top surface. The device also includes a P-doped well formed in the semiconductor substrate and extending downwardly from the top surface. The device includes a cathode of a diode formed by an N-doped region in the P-doped well. The device also includes an anode of the diode formed by a P-doped region, the P-doped region spaced away from the N-doped region in the P-doped well. The device includes a deep N-type buried layer (DNBL) formed in the semiconductor substrate, the P-doped well formed between the top surface and the DNBL. The device also includes an N-doped well extending from the top surface to the DNBL.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Inventors: Siva Kumar SUDANI, Jerry L. DOORENBOS, YuGuo WANG, Srinivas Kumar PULIJALA, Bharath Karthik VASAN
  • Publication number: 20230268897
    Abstract: A device comprises a voltage limiter, two capacitors, a resistor, and a voltage follower buffer. The voltage limiter has a first input coupled to a reference voltage rail, a second input coupled to a supply voltage rail, and two voltage limiter outputs. The first capacitor is coupled between a device output and the first voltage limiter output, and the resistor is coupled between the first and second voltage limiter outputs. The voltage follower buffer has an input coupled to the first voltage limiter output and a voltage follower buffer output. The second capacitor is coupled between a device input and the voltage follower buffer output. In some implementations, a resistance of the resistor is greater than a capacitance of the first capacitor. In some implementations, a third capacitor is coupled between the device input and the device output.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Inventors: Vadim Valerievich IVANOV, Srinivas Kumar PULIJALA
  • Publication number: 20230246605
    Abstract: In an example, a system includes an amplifier having an output stage configured to provide an output voltage, where the output stage includes a p-channel transistor and an n-channel transistor. The system includes a sense transistor having a gate coupled to a gate of the p-channel transistor, where the sense transistor is configured to sense a current of the p-channel transistor and produce a sense current. The system includes a current mirror coupled to the sense transistor and configured to provide the sense current to a gate of a control transistor, the control transistor having a source coupled to the gate of the p-channel transistor. The system includes a reference current source coupled to the control transistor and configured to provide a reference current. The control transistor is configured to adjust a gate current provided to the p-channel transistor based on comparing the sense current to the reference current.
    Type: Application
    Filed: January 31, 2022
    Publication date: August 3, 2023
    Inventors: Vivek VARIER, Srinivas Kumar PULIJALA, Vadim Valerievich IVANOV, Jerry L. DOORENBOS
  • Publication number: 20230208652
    Abstract: An Internet of Things (IoT) device with zero touch provisioning includes one or more processing devices; a secure element; and memory storing software that, when executed in the one or more processing devices, cause the one or more processing devices to: install one or more clients on the IoT device for provisioning, enrollment, and updating, based on a device configuration; store an immutable device identity and a signing certificate in the secure element; and responsive to the IoT device being powered-on, cause the one or more clients and the secure element to perform the zero touch provisioning of the IoT device. The one or more clients on the IoT device for provisioning, enrollment, and updating operate with corresponding services with all communicating being encrypted, thereby protecting against cloning and counterfeiting of IoT devices.
    Type: Application
    Filed: February 20, 2023
    Publication date: June 29, 2023
    Inventors: Srinivas Kumar, Atul Gupta, Shreya Uchil, Ruslan Ulanov, Srikesh Amrutur Srinivas
  • Patent number: 11689210
    Abstract: An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a se
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: June 27, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Prasanth K, Srinivas Kumar Reddy Naru, Visvesvaraya Appala Pentakota
  • Publication number: 20230138266
    Abstract: An example apparatus includes: an analog input; a resistor circuit including a first reference output and a second reference output; a first amplifier including a first analog input, a first reference input, and a first amplifier output, the first analog input coupled to the analog input, the first reference input coupled to the first reference output; a second amplifier including a second analog input, a second reference input, and a second amplifier output, the second analog input coupled to the analog input, the second reference input coupled to the second reference output; a first comparator including a first comparator input, the first comparator input coupled to the first amplifier output; and a second comparator including a second comparator input, the second comparator input coupled to the second amplifier output; a first multiplexer including a first multiplexer input and a first residue output, the first multiplexer input coupled to the first amplifier output; and a second multiplexer including a se
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Prasanth K, Srinivas Kumar Reddy Naru, Visvesvaraya Appala Pentakota
  • Publication number: 20230118397
    Abstract: In examples of a chopper operational amplifier, a current control circuit comprises a pair of voltage sources, each of which may be varied to generate a voltage signal of a particular value, and multiple inverters, each of which is configured to receive either a clock signal or its complement signal and one of the voltage signals. Based on these inputs, each inverter generates a control signal that is delivered to a corresponding switch in the input stage of the chopper operational amplifier to control the gate voltage of that switch. Based on the difference between the values of the voltage signals, the current control circuit operates to reduce the amplitudes of base currents induced by charge injection at the input terminals of the chopper operational amplifier.
    Type: Application
    Filed: October 14, 2021
    Publication date: April 20, 2023
    Inventors: VADIM VALERIEVICH IVANOV, Srinivas Kumar Pulijala
  • Publication number: 20230092097
    Abstract: An example apparatus includes: a folded cascode circuit including a first input terminal, a second input terminal, a first output terminal, and a second output terminal; a first feedback loop including a third output terminal, the third output terminal coupled to the first output terminal; a second feedback loop including a fourth output terminal, the fourth output terminal coupled to the second output terminal; and a first driver including a first control terminal and a fifth output terminal, the first control terminal coupled to the third output terminal; and a second driver including a second control terminal and a sixth output terminal, the second control terminal coupled to the fourth output terminal, the sixth output terminal coupled to the fifth output terminal.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Vadim Valerievich Ivanov, Srinivas Kumar Pulijala, Piyush Deepak Kaslikar
  • Publication number: 20230082872
    Abstract: In an example, a system includes an input channel and a voltage to delay converter (V2D) coupled to the input channel. The system also includes a first multiplexer coupled to the V2D and an analog-to-digital converter (ADC) coupled to the first multiplexer. The system includes a second multiplexer coupled to the input channel and an auxiliary ADC coupled to the second multiplexer. The system includes calibration circuitry coupled to an output of the auxiliary ADC, where the calibration circuitry is configured to correct a non-linearity in a signal provided by the input channel. The calibration circuitry is also configured to determine the non-linearity of the signal provided to the ADC relative to the signal provided to the auxiliary ADC.
    Type: Application
    Filed: January 31, 2022
    Publication date: March 16, 2023
    Inventors: Nagarajan VISWANATHAN, Himanshu VARSHNEY, Vinam ARORA, Charls BABU, Srinivas Kumar NARU
  • Publication number: 20230065060
    Abstract: A trust chain having client system and a remote system in a secure connection, wherein an intermediary system associated with the network flow path serves as a signing entity to establish an end to end transitive trust. The intermediate system is a corroborative entity in the operations technology realm of the client system. The remote system serves as the host for a plurality of services in the information technology realm. A two way handshake during the initial secure exchange protocol between a local client application and a remote service is extended to a three way handshake that includes a nonce issued by the remote service on the remote system and a digital signature for the nonce issued by a signature service on an associated intermediate system. The nonce signature is verified authoritatively at the remote system based on the signing certificate of the intermediate system for explicit proof of association.
    Type: Application
    Filed: April 11, 2022
    Publication date: March 2, 2023
    Inventors: Srinivas KUMAR, Shashank Jaywant PANDHARE, Atul GUPTA, Gopal RAMAN
  • Patent number: 11595217
    Abstract: For zero-touch provisioning of devices at scale using device configuration templates by device type, a secure element, a provisioning wizard, a provisioning client, an enrollment client, an update client, an enrollment service, an update publisher service, signing and encryption certificates, a method including generating device configuration templates for enrollment and update by device type, sending device configuration templates signed with a device owner signing certificate, and a device owner encryption certificate to the device manufacturer, generating a device configuration for a device based on the device configuration templates using a secure element on the device for immutable device identity, an extended configuration for the device, signing the device configuration with a device manufacturer signing certificate and a secure element signing certificate, encrypting the doubly signed device configuration with an owner encryption certificate, configuring bootstrap metadata, and configuring the device
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: February 28, 2023
    Assignee: DigiCert, Inc.
    Inventors: Srinivas Kumar, Atul Gupta, Shreya Uchil, Ruslan Ulanov, Srikesh Amrutur Srinivas
  • Patent number: 11573956
    Abstract: A system, method, and computer-readable medium for proving feedback on database instructions, identifying, for example, existing patterns and providing suggested replacement instructions. This may have the effect of improving the efficiency of instructions used to create and/or manipulate databases. According to some aspects, these and other benefits may be achieved by parsing received instructions into an organizational structure, traversing the organizational structure for known patterns, and suggesting replacement patterns. In implementation, this may be effected by receiving one or more sets of known patterns and corresponding replacement patterns, parsing received instructions, comparing the known patterns with the parsed instructions, and providing suggested replacement patterns based on one or more known patterns matching the parsed instructions. A benefit of may include reducing Cartesian products during the merging of tables.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 7, 2023
    Assignee: Capital One Services, LLC
    Inventors: Dennis J. Mire, Puneet Goyal, Siddharth Gupta, Srinivas Kumar, Deepak Sundararaj, Oron Hazi
  • Publication number: 20230034632
    Abstract: Differential input circuits employ protection transistors and feedback paths to limit the differential voltage applied to input transistors. In an example arrangement, a differential input voltage is applied to terminals of the protection transistors, and current paths couple the respective protection transistors to control terminals of the input transistors, respectively. A control terminal drive voltage source is coupled to the control terminals of the input protection transistors to control the drive voltage applied to those terminals. Feedback paths, one for each of the input transistors, control voltages applied to the control terminals of the input transistors, maintaining the input differential voltage at a relatively low level and defined by the product of a specified current value and a specified resistance value.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 2, 2023
    Inventors: Vadim Valerievich Ivanov, Srinivas Kumar Pulijala
  • Patent number: 11551159
    Abstract: Generally, the present disclosure is directed to systems and methods for performing task-oriented response generation that can provide advantages for artificial intelligence systems or other computing systems that include natural language processing for interpreting user input. Example implementations can process natural language descriptions of various services that can be accessed by the system. In response to a natural language input, systems can identify relevant values for executing one of the service(s), based in part on comparing embedded representations of the natural language input and the natural language description using a machine learned model.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: January 10, 2023
    Assignee: GOOGLE LLC
    Inventors: Abhinav Kumar Rastogi, Raghav Gupta, Xiaoxue Zang, Srinivas Kumar Sunkara, Pranav Khaitan