Patents by Inventor Srinivas Perisetty
Srinivas Perisetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11665031Abstract: A method for tuning an analog front end response is provided. The method includes determining a peaking control value for an analog front end (AFE) of a receiver, determining an attribute corresponding to the peaking control value, selecting the peaking control value as the operating peaking control value for the AFE based on the attribute being determined to be higher than a previous attribute, and performing a receiver adaptation using the peaking control for a one or more transmitter configurations.Type: GrantFiled: October 5, 2021Date of Patent: May 30, 2023Assignee: SYNOPSYS, INC.Inventors: Srinivas Perisetty, Jayabharath Reddy Madi Reddy, Suresh Nagula, Philip Michael Chopp
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Patent number: 10200037Abstract: A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.Type: GrantFiled: July 10, 2017Date of Patent: February 5, 2019Assignee: Altera CorporationInventor: Srinivas Perisetty
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Publication number: 20170373690Abstract: A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.Type: ApplicationFiled: July 10, 2017Publication date: December 28, 2017Inventor: Srinivas Perisetty
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Patent number: 9735779Abstract: A field programmable gate array (FPGA) includes a temperature sensor array. The FPGA also includes a supply voltage modulation circuit. The supply voltage modulation circuit is coupled to the temperature sensor array.Type: GrantFiled: July 31, 2009Date of Patent: August 15, 2017Assignee: Altera CorporationInventor: Srinivas Perisetty
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Patent number: 9496268Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: GrantFiled: May 2, 2014Date of Patent: November 15, 2016Assignee: Altera CorporationInventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Publication number: 20160232952Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: ApplicationFiled: May 2, 2014Publication date: August 11, 2016Inventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Publication number: 20150318029Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: ApplicationFiled: May 2, 2014Publication date: November 5, 2015Inventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Publication number: 20140258956Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.Type: ApplicationFiled: May 19, 2014Publication date: September 11, 2014Applicant: Altera CorporationInventors: David Lewis, Christopher Lane, Sarathy Partha Sribhashyam, Srinivas Perisetty, Tim Vanderhoek, Vaughn Betz, Thomas Yau-Tsun Wong, Andy L. Lee
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Patent number: 8750026Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: GrantFiled: June 20, 2013Date of Patent: June 10, 2014Assignee: Altera CorporationInventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Patent number: 8732635Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.Type: GrantFiled: July 1, 2008Date of Patent: May 20, 2014Assignee: Altera CorporationInventors: David Lewis, Christopher F. Lane, Sarathy Sribhashyam, Srinivas Perisetty, Tim Vanderhoek, Vaughn Betz, Thomas Yau-Tsun Wong, Andy L. Lee
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Patent number: 8711614Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.Type: GrantFiled: March 21, 2011Date of Patent: April 29, 2014Assignee: Altera CorporationInventors: Andy L. Lee, Irfan Rahim, Lu Zhou, Madhuri Mailavaram, Srinivas Perisetty
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Patent number: 8618786Abstract: Integrated circuits with voltage regulation circuitry are provided. Voltage regulation circuitry may be powered by a core supply voltage and may not have a bandgap reference circuit. Voltage regulation circuitry may have an error amplifier in a negative feedback configuration. The error amplifier may have inputs connected to reference voltages generated by resistor strings. The resistor strings may be trimmable to provide a desired negative voltage. The desired negative voltage may be fed to the gates of transistors to help reduce leakage. The desired negative voltage may be have improved tolerance to process-voltage-temperature variations and may improve the reliability of transistors.Type: GrantFiled: August 31, 2009Date of Patent: December 31, 2013Assignee: Altera CorporationInventors: Srinivas Perisetty, Arvind Sherigar
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Patent number: 8482963Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: GrantFiled: December 2, 2009Date of Patent: July 9, 2013Assignee: Altera CorporationInventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Patent number: 8369175Abstract: Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.Type: GrantFiled: September 1, 2010Date of Patent: February 5, 2013Assignee: Altera CorporationInventors: Lin-Shih Liu, Andy L. Lee, Ping-Chen Liu, Irfan Rahim, Srinivas Perisetty
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Patent number: 8279660Abstract: Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate power supply voltage during reading and writing operations. Each memory element may contain circuitry to select between power supply voltages during reading and writing operations. During reading operations, an elevated voltage may power cross-coupled inverters that store data in the memory elements while a non-elevated voltage may be used to turn on associated address transistors. During writing operations, the non-elevated voltage may power the cross-coupled inverters while the elevated voltage may be used to turn on the associated address transistors.Type: GrantFiled: May 5, 2011Date of Patent: October 2, 2012Assignee: Altera CorporationInventor: Srinivas Perisetty
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Patent number: 8099704Abstract: Methods and systems to improve performance in an Integrated Circuit (IC) are presented. The method includes performing a timing analysis for a circuit design of an IC. The modules in the circuit design use a standard voltage bias by default. In one embodiment, the timing analysis is performed by a circuit design tool. The method then identifies a critical path in the timing analysis, where a signal propagating through the critical path does not meet timing requirements for the circuit design. The method then selects a module of the IC in the critical path to apply a high speed voltage bias to the body of transistors in the module, resulting in a smaller propagation delay thorough the selected module than if the standard voltage bias were applied to the selected module, thus allowing the circuit design to meet the timing requirements.Type: GrantFiled: July 28, 2008Date of Patent: January 17, 2012Assignee: Altera CorporationInventor: Srinivas Perisetty
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Publication number: 20110211384Abstract: Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate power supply voltage during reading and writing operations. Each memory element may contain circuitry to select between power supply voltages during reading and writing operations. During reading operations, an elevated voltage may power cross-coupled inverters that store data in the memory elements while a non-elevated voltage may be used to turn on associated address transistors. During writing operations, the non-elevated voltage may power the cross-coupled inverters while the elevated voltage may be used to turn on the associated address transistors.Type: ApplicationFiled: May 5, 2011Publication date: September 1, 2011Inventor: Srinivas Perisetty
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Patent number: 7990664Abstract: An ESD protection circuit is integrated into the core of an FPGA in a distributed fashion coupling the bodies of one or more transistors to the power supply pin and/or the ground pin of the FPGA. The ESD protection circuit includes one or more positive discharge paths and one or more negative discharge paths. In the case of a positive ESD event, the positive discharge paths are on and the negative discharge paths are off. In the case of a negative ESD event, the positive discharge paths are off and the negative discharge paths are on. In either event, the bodies of the transistors track the voltages at the power supply pin and/or the ground pin to protect the core from being by damaged by electrostatic discharge.Type: GrantFiled: December 14, 2006Date of Patent: August 2, 2011Assignee: Altera CorporationInventors: Srinivas Perisetty, Antonio Gallerano, Jeffrey T. Watt, Cheng-Hsiung Huang
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Patent number: 7978450Abstract: An integrated circuit has pins to which electrostatic discharge voltages may be delivered during electrostatic discharge events. Circuitry in the integrated circuit can be protected from damage by the electrostatic discharge voltages by electrostatic discharge protection circuitry. The electrostatic discharge protection circuitry may include one or more diodes that are connected between a given pin and ground to discharge negative electrostatic discharge voltages. Positive electrostatic discharge voltages may be discharged using a transistor that is connected between the pin and ground and that breaks down at a breakdown voltage. A voltage blocking circuit such as a circuit based on a voltage blocking transistor may be used to prevent damaging electrostatic discharge voltages from reaching sensitive circuitry. Pull down circuitry may be used to help ensure that the circuitry is protected from damage during electrostatic discharge events.Type: GrantFiled: March 20, 2008Date of Patent: July 12, 2011Assignee: Altera CorporationInventor: Srinivas Perisetty
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Patent number: 7957177Abstract: Dual port memory elements and memory array circuitry that utilizes elevated and non-elevated power supply voltages for performing reliable reading and writing operations are provided. The memory array circuitry may contain circuitry to switch a power supply line of a column of memory elements in the array to an appropriate power supply voltage during reading and writing operations. Each memory element may contain circuitry to select between power supply voltages during reading and writing operations. During reading operations, an elevated voltage may power cross-coupled inverters that store data in the memory elements while a non-elevated voltage may be used to turn on associated address transistors. During writing operations, the non-elevated voltage may power the cross-coupled inverters while the elevated voltage may be used to turn on the associated address transistors.Type: GrantFiled: June 5, 2008Date of Patent: June 7, 2011Assignee: Altera CorporationInventor: Srinivas Perisetty