Patents by Inventor Sriram Natarajan

Sriram Natarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220280281
    Abstract: A method of making a self-sealing membrane for a prosthetic implant includes applying tension to a first layer of a cured elastomeric material to stretch the first layer, and while the first layer remains stretched, applying a second layer of an uncured elastomeric material over a first major surface of the first layer. After the second layer is cured, the tension on the first layer is released, whereupon the first layer returns to a non-stretched configuration for holding the second layer in contraction. The method includes, while the first layer remains stretched, applying a third layer of an uncured elastomeric material over a second major surface of the first layer. After curing the second and third layers, tension is released from the first layer, which returns to the non-stretched configuration for holding the second and third layers in contraction.
    Type: Application
    Filed: February 18, 2022
    Publication date: September 8, 2022
    Inventors: Michael Hoffman, Sriram Natarajan, Annmarie Mullen, Hector Javier Toro Estrella
  • Patent number: 11403536
    Abstract: A system and method for anti-pattern detection for computing application prior to deployment in cloud environment is provided. The present invention provides for applying a pre-defined set of rules on one or more applications source code. The pre-defined set of rules are applied in pre-defined order. Further, applying one or more anti-pattern detection models on one or more applications source code. The anti-pattern detection models are applied for determining correlation between one or more syntax patterns of the application source code and the anti-patterns detection models. Further, detecting anti-patterns associated with the syntax patterns of the application source code based on the pre-defined set of rules and the anti-patterns detection models. The detected anti-patterns represent unique anti-patterns. Lastly, generating a migration actionable event for the application source code based on the detected anti-patterns.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 2, 2022
    Assignee: COGNIZANT TECHNOLOGY SOLUTIONS INDIA PVT. LTD.
    Inventors: Parasu Pillai Iyappan Velammal, Duraivel Kalyanasundaram, Sriram Venkatakrishnan, Selvaraj Natarajan, Janakiraman Ramani
  • Patent number: 11341753
    Abstract: A method for detecting the presence of an emergency vehicle includes receiving a plurality of image frames over a period of time, determining an EV colour component for each image frame based on the ratio of a first colour relative to the total colour in each pixel and assigning to a pixel a first value if the EV colour component exceeds a predefined threshold value and a second value if the EV colour component does not, and determining for an EV colour value for the first colour based on the sum of all of the first values for each image frame. The method also includes generating a time domain representation, converting the time domain representation for the plurality of image frames to a frequency spectrum, and determining if any flashing light sources of the first colour associated with one or more types of emergency vehicles is present.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 24, 2022
    Assignee: CONTINENTAL AUTOMOTIVE GMBH
    Inventors: Vishnu Vardhana Asvatha Narayanan, Sreekanth Velladath, Sriram Natarajan, Sri Hari Bhupala Haribhakta, Elias Strigel, Martin Pfitzer
  • Patent number: 11302405
    Abstract: A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventors: Sriram Natarajan, Shankar Natarajan, Yihua Zhang, Hinesh K. Shah, Rohit S. Shenoy, Arun Sitaram Athreya
  • Patent number: 11145389
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Sriram Natarajan, Arun S. Athreya, Venkata S. Surampudi
  • Patent number: 11119672
    Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: September 14, 2021
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Suresh Nagarajan, Shivashekar Muralishankar, Sriram Natarajan, Yihua Zhang
  • Patent number: 10877686
    Abstract: An apparatus is described that includes a solid state drive having non volatile buffer memory and non volatile primary storage memory. The non volatile buffer memory is to store less bits per cell than the non volatile primary storage memory. The solid state drive includes a controller to flush the buffer in response to a buffer flush command received from a host. The controller is to cause the solid state drive to service read/write requests that are newly received from the host in between flushes of smaller portions of the buffer's content that are performed to service the buffer flush command.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Romesh Trivedi, Suresh Nagarajan, Sriram Natarajan
  • Publication number: 20200167089
    Abstract: An embodiment of a memory controller device includes technology to control access to a memory array which includes a single-level cell region and a multi-level cell region, determine an amount of valid data in a dynamic portion of the single-level cell region at runtime, and adjust a size of the dynamic portion of the single-level cell region at runtime based on the determined amount of valid data in the dynamic portion of the single-level cell region. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: August 6, 2019
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Shankar Natarajan, Suresh Nagarajan, Shivashekar Muralishankar, Sriram Natarajan, Yihua Zhang
  • Patent number: 10650886
    Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya, Romesh B. Trivedi
  • Publication number: 20200118637
    Abstract: A nonvolatile (NV) memory device includes an NV storage media and a storage controller to control access to the NV storage media. In response to a host read request, the storage controller can determine if the NV storage media is in a stable Vt (threshold voltage) state. If the NV storage media is in a stable Vt state, the storage controller can perform a reset read operation prior to servicing the host read request. A reset read is a read operation that does not produce data to send back to the host. The reset read operation is a dummy read that puts the NV storage media into a transient Vt state, which has lower risk of read disturb.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: Sriram NATARAJAN, Shankar NATARAJAN, Yihua ZHANG, Hinesh K. SHAH, Rohit S. SHENOY, Arun Sitaram ATHREYA
  • Publication number: 20200118636
    Abstract: Techniques for preventing read disturb in NAND memory devices are described. In one example, reads are tracked for sub-groups. When the number of reads to a sub-group meets a threshold, the data at the wordline on which the threshold was met is moved along with the data at neighboring wordlines to an SLC block without moving the entire block. The performance impact and write amplification impact of read disturb mitigation can be significantly reduced while maintaining some data continuity.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Arun Sitaram ATHREYA, Shankar NATARAJAN, Sriram NATARAJAN, Yihua ZHANG, Suresh NAGARAJAN
  • Publication number: 20200110949
    Abstract: A method for detecting the presence of an emergency vehicle includes receiving a plurality of image frames over a period of time, determining an EV colour component for each image frame based on the ratio of a first colour relative to the total colour in each pixel and assigning to a pixel a first value if the EV colour component exceeds a predefined threshold value and a second value if the EV colour component does not, and determining for an EV colour value for the first colour based on the sum of all of the first values for each image frame. The method also includes generating a time domain representation, converting the time domain representation for the plurality of image frames to a frequency spectrum, and determining if any flashing light sources of the first colour associated with one or more types of emergency vehicles is present.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 9, 2020
    Inventors: Vishnu Vardhana Asvatha Narayanan, Sreekanth Velladath, Sriram Natarajan, Sri Hari Bhupala Haribhakta, Elias Strigel, Martin Pfitzer
  • Publication number: 20200105363
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control a persistent storage media including a first media to store one or more source blocks of data and a second media to store one or more destination blocks of data, determine if an error rate associated with a read of a particular destination block of the one or more destination blocks exceeds a threshold error rate, identify a particular source block of the one or more source blocks which corresponds to erroneous data in the particular destination block, determine which of the particular source block and the particular destination block is a failed block, and retire the failed block. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Shankar Natarajan, Sriram Natarajan, Arun S. Athreya, Venkata S. Surampudi
  • Patent number: 10469320
    Abstract: A versioning system for network state of a network includes: a server, configured to execute a versioning controller, the versioning controller being configured to communicate with a plurality of data plane devices of the network and store a plurality of network states in a local non-transitory memory corresponding to the server, wherein the plurality of network states stored in the local non-transitory memory include a current authoritative network state and a plurality of previous network states each corresponding to a modification of a flow within the network; and the plurality of data plane devices, configured to notify the server of flow modifications made by respective data plane devices and to receive the current authoritative network state from the server.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: November 5, 2019
    Assignees: DEUTSCHE TELEKOM AG, UNIVERSITY OF MASSACHUSETTS, INFINERA CORPORATION
    Inventors: Abhishek Dwaraki, Sriram Natarajan, Tilman Wolf, Srini Seetharaman
  • Publication number: 20190267080
    Abstract: Systems, apparatuses and methods may provide for technology to determine a programmable eviction ratio associated with a storage device and convert a portion of a single-level cell region in the storage device into a multi-level cell region in accordance with the programmable eviction ratio. In one example, the amount of the portion converted into the multi-level cell region varies gradually as a function of percent capacity filled in the storage device.
    Type: Application
    Filed: February 28, 2019
    Publication date: August 29, 2019
    Inventors: Shankar Natarajan, Sriram Natarajan, Suresh Nagarajan, Ramkarthik Ganesan, Arun S. Athreya, Romesh B. Trivedi
  • Patent number: 10379782
    Abstract: Systems, apparatuses and methods may provide for technology that writes a block of data addressed within a host managed cache region into a set of multi-level non-volatile memory (NVM) cells organized into a dynamic single level cell buffer region, that writes a block of data addressed outside the host managed cache region into the set of multi-level NVM cells organized into a static single level cell buffer region, and automatically writes the contents of the static single level cell buffer region into the dynamic multi-level NVM media region. The host manage cache region comprises a set of dynamic single level NVM cells within the dynamic multi-level NVM media region, and the multi-level NVM cells are to be dynamically convertible into and from single NVM cells.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Suresh Nagarajan, Sriram Natarajan, Shankar Natarajan, Jason B. Akers
  • Patent number: 10300479
    Abstract: The present disclosure provides apparatuses, systems, and methods involving a spotter apparatus for depositing a substance from a carrier fluid onto a deposition surface in an ordered array. The spotter apparatus includes a loading surface, including a first well and a second well, and a different outlet surface, including a first opening and a second opening, where a first microconduit fluidly couples the first well with the first opening and a second microconduit fluidly couples the second well with the second opening. An overlay is sealed to the outlet surface and penetrated by a deposition channel that is situated to communicate carrier fluid among the first opening, the second opening, and the deposition surface when the overlay is pressed against the deposition surface.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 28, 2019
    Assignee: Carterra, Inc.
    Inventors: Bruce Kent Gale, Adam Miles, Joshua Wayne Eckman, Sriram Natarajan, Jim Smith, Mark Eddings
  • Patent number: 10300450
    Abstract: The present disclosure provides apparatuses, systems, and methods involving a spotter for depositing a substance on a submerged surface. The spotter comprises an outlet cavity defined at least in part by a spotting orifice, a first opening, and a second opening. The spotter also comprises a first conduit fluidly coupled to the first opening and a second conduit fluidly coupled to the second opening. The spotter is adapted so that fluid flowing through the first conduit and the second conduit is communicated among the first opening, the second opening, and a submerged deposition surface when the sealing orifice is sealed against the submerged deposition surface to form a deposition spot on the submerged deposition surface. The submerged deposition surface is within a liquid such that the liquid covers the deposition spot upon removal of the orifice from the deposition surface.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 28, 2019
    Assignee: Carterra, Inc.
    Inventors: Bruce K. Gale, Joshua W. Eckman, Adam Miles, Christopher Morrow, James Smith, Sriram Natarajan, Mark Eddings
  • Patent number: 10278701
    Abstract: An implant having an adhesive structure comprising a planar surface having two sides and rectangular cuboid-based protrusions having pyramidal tips extending from at least one of said sides, optionally having a porous basic supporting structure, and methods of making and using such implants.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 7, 2019
    Assignees: ETHICON, INC., AGENCY FOR SCIENCE TECHNOLOGY AND RESEARCH
    Inventors: Sriram Natarajan, Joseph J. Hammer, Kevin Cooper, Murty Vyakarnam, Hong Yee Low, Isabel Rodriguez, Chee Tiong Lim, Audrey Yoke Yee Ho
  • Patent number: 10242753
    Abstract: A method of measuring a subject's strength of associations of multidimensional traits involving each of a first pair of first and second categories with each of a second pair of third and fourth categories includes selecting a first target concept for the first category and a second target concept for the second category and selecting a first trait for the third category and, for the fourth category, a plurality of alternative traits to provide a basis for contrasting with the first trait. The method further includes having the subject respond to a first set of trials in a first manner when there is presented an exemplar of either the first category or the third category and in a second manner when there is presented an exemplar of either the second category or the fourth category and presenting the subject with a first series of exemplars in the first set of trials, the first series including exemplars in all four categories.
    Type: Grant
    Filed: August 18, 2006
    Date of Patent: March 26, 2019
    Assignee: University of Washington
    Inventors: Anthony G. Greenwald, Sriram Natarajan