Patents by Inventor Stanley Hong

Stanley Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ADAPTIVE HIGH VOLTAGE CIRCUITRY AND METHODS FOR PROGRAMMING OPERATIONS IN AN ANALOG NEURAL MEMORY ARRAY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200058357
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. The system can modify a high voltage signal applied to an array of cells during a programming operation as the number of cells being programmed changes.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 20, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • ADJUSTABLE CURRENT SINK TO DRAW COMPENSATION CURRENT FROM HIGH VOLTAGE GENERATION CIRCUITRY DURING PROGRAMMING OPERATION OF ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200051635
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 13, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • CURRENT COMPENSATION BLOCK AND METHOD FOR PROGRAMMING ANALOG NEURAL MEMORY IN DEEP LEARNING ARTIFICIAL NEURAL NETWORK
    Publication number: 20200051636
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Application
    Filed: August 25, 2019
    Publication date: February 13, 2020
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Redundant Memory Access For Rows Or Columns Containing Faulty Memory Cells In Analog Neural Memory In Deep Learning Artificial Neural Network
    Publication number: 20200019849
    Abstract: Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.
    Type: Application
    Filed: October 3, 2018
    Publication date: January 16, 2020
    Inventors: Hieu Van Tran, Stanley Hong, Thuan Vu, Anh Ly, Hien Pham, Kha Nguyen, Han Tran
  • Method and apparatus for high voltage generation for analog neural memory in deep learning artificial neural network
    Patent number: 10522226
    Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: December 31, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stanley Hong, Anh Ly, Vipin Tiwari, Nhan Do
  • Decoders For Analog Neural Memory In Deep Learning Artificial Neural Network
    Publication number: 20190286976
    Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.
    Type: Application
    Filed: May 29, 2018
    Publication date: September 19, 2019
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han TRan
  • Programmable Neuron For Analog Non-Volatile Memory In Deep Learning Artificial Neural Network
    Publication number: 20190205729
    Abstract: Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.
    Type: Application
    Filed: March 27, 2018
    Publication date: July 4, 2019
    Inventors: Hieu Van Tran, Stanley Hong, Anh Ly, Thuan Vu, Hien Pham, Kha Nguyen, Han Tran
  • High Precision And Highly Efficient Tuning Mechanisms And Algorithms For Analog Neuromorphic Memory In Artificial Neural Networks
    Publication number: 20190164617
    Abstract: An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.
    Type: Application
    Filed: November 29, 2017
    Publication date: May 30, 2019
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do, Steven Lemke, Santosh Hariharan, Stanley Hong
  • Methods For Writing To An Array Of Resistive Random Access Memory Cells
    Publication number: 20190080754
    Abstract: Numerous embodiments of methods for writing to a resistive random access memory (RRAM) cell are disclosed. In one embodiment, the system verifies if a current through the RRAM cell exceeds a threshold value, and if it does not, the system executes a concurrent write-while-verify operation. In another embodiment, the system verifies if current through the RRAM cell has reached a target value, and if it has not, the system executes a write operation and then verifies the write operation using a current comparison.
    Type: Application
    Filed: August 31, 2018
    Publication date: March 14, 2019
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
  • Architectures and Layouts for an Array Of Resistive Random Access Memory Cells and Read and Write Methods Thereof
    Publication number: 20190080753
    Abstract: Various architectures and layouts for an array of resistive random access memory (RRAM) cells are disclosed. The RRAM cells are organized into rows and columns, with each cell comprising a top electrode, a bottom electrode, and a switching layer. Circuitry is included for improving the reading and writing of the array, including the addition of a plurality of columns of dummy RRAM cells in the array used as a ground source, connecting source lines to multiple pairs of rows of RRAM cells, and the addition of rows of isolation transistors.
    Type: Application
    Filed: September 11, 2017
    Publication date: March 14, 2019
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
  • Sense Amplifier Circuit For Reading Data In A Flash Memory Cell
    Publication number: 20190066805
    Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.
    Type: Application
    Filed: August 25, 2017
    Publication date: February 28, 2019
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong
  • Sense amplifier circuit for reading data in a flash memory cell
    Patent number: 10199112
    Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: February 5, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong
  • Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
    Patent number: 7656708
    Abstract: The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: February 2, 2010
    Assignee: Atmel Corporation
    Inventors: Stanley Hong, Jami Wang, Alan Chen
  • MEMORY ARCHITECTURE WITH ADVANCED MAIN-BITLINE PARTITIONING CIRCUITRY FOR ENHANCED ERASE/PROGRAM/VERIFY OPERATIONS
    Publication number: 20080031075
    Abstract: The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line.
    Type: Application
    Filed: October 12, 2007
    Publication date: February 7, 2008
    Applicant: ATMEL CORPORATION
    Inventors: Stanley Hong, Jami Wang, Alan Chen
  • Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
    Patent number: 7295485
    Abstract: The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: November 13, 2007
    Assignee: Atmel Corporation
    Inventors: Stanley Hong, Jami Wang, Alan Chen
  • Individually portioned packaged food product and method for manufacturing the same
    Publication number: 20070042088
    Abstract: A reformulated food product which may include a food which has been comminuted, and mixed or blended with additional ingredients and filled into a cylindrical web. The web is flattened and all of the openings are hermetically sealed. The transverse hermetic seals divide the product into individual portions, and the individual portions may either be joined to each other to form a group of portions, or separated into individual portions by cutting the web at the transverse seals.
    Type: Application
    Filed: August 17, 2005
    Publication date: February 22, 2007
    Inventors: Susan Frinak, Stanley Hong, Franco Milani
  • Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations
    Publication number: 20070014179
    Abstract: The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line.
    Type: Application
    Filed: July 12, 2005
    Publication date: January 18, 2007
    Inventors: Stanley Hong, Jami Wang, Alan Chen