Abstract: An apparatus includes a flow cell body, a plurality of electrodes, an imaging assembly, and one or more barrier features. The flow cell body defines one or more flow channels and a plurality of wells defined as recesses in the floor of each flow channel. Each well is fluidically coupled with the corresponding flow channel. The flow cell body further defines interstitial surfaces between adjacent wells. Each well defines a corresponding depth. Each electrode is positioned in a corresponding well of the plurality of wells. The electrodes are to effect writing of polynucleotides in the wells. The imaging assembly is to capture images of polynucleotides written in the wells. The one or more barrier features are positioned in the wells, between the wells, or above the wells. The one or more barrier features contain reactions in each well, reduce diffusion between the wells, or reduce optical cross-talk between the wells.

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Two or more physical memory cells are grouped together to form a logical cell that stores one of N possible levels. Within each logical cell, the memory cells can be programmed using different mechanisms. For example, one or more of the memory cells in a logical cell can be programmed using a coarse programming mechanism, one or more of the memory cells can be programmed using a fine mechanism, and one or more of the memory cells can be programmed using a tuning mechanism. This achieves extreme programming accuracy and programming speed.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

Abstract: An apparatus includes a flow cell body, a plurality of electrodes, an imaging assembly, and one or more barrier features. The flow cell body defines one or more flow channels and a plurality of wells defined as recesses in the floor of each flow channel. Each well is fluidically coupled with the corresponding flow channel. The flow cell body further defines interstitial surfaces between adjacent wells. Each well defines a corresponding depth. Each electrode is positioned in a corresponding well of the plurality of wells. The electrodes are to effect writing of polynucleotides in the wells. The imaging assembly is to capture images of polynucleotides written in the wells. The one or more barrier features are positioned in the wells, between the wells, or above the wells. The one or more barrier features contain reactions in each well, reduce diffusion between the wells, or reduce optical cross-talk between the wells.

Abstract: Various algorithms are disclosed for verifying the stored weight in a non-volatile memory cell in a neural network following a multilevel programming operation of the non-volatile memory cell by converting the stored weight into a plurality of digital output bits. Circuity, such as an adjustable reference current source, for implementing the algorithms are disclosed.

Abstract: Numerous embodiments for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. High voltage circuits used to generate high voltages applied to terminals of the non-volatile memory cells during the precision tuning process are also disclosed. Programming sequences for the application of the voltages to the terminals to minimize the occurrence of disturbances during tuning are also disclosed.

Abstract: Numerous embodiments of an improved charge pump design are disclosed for generating the high voltages necessary to perform erase and program operations in non-volatile flash memory devices. In these embodiments, each boost stage in the charge pump is modified to overcome a deficiency in prior art charge pumps whereby voltage actually would decrease in the final boost stage. These modifications include the addition of one or more of a clock doubling circuit, a local self-precharge circuit, a feed-forward precharge circuit, a feed-backward precharge circuit, and a hybrid circuit comprising NMOS and PMOS transistors and diodes.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, wherein within each adjacent pair one column in the adjacent pair comprises cells storing W+ values and one column in the adjacent pair comprises cells storing W? values, wherein adjacent cells in the adjacent pair store a differential weight, W, according to the formula W=(W+)?(W?). In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W? values.

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.

Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

Abstract: An apparatus includes a flow cell body, a plurality of electrodes, an integrated circuit, and an imaging assembly. The flow cell body defines one or more flow channels and a plurality of wells. Each flow channel is configured to receive a flow of fluid. Each well is fluidically coupled with the corresponding flow channel. Each well is configured to contain at least one polynucleotide. Each electrode is positioned in a corresponding well of the plurality of wells. The electrodes are operable to effect writing of polynucleotides in the corresponding wells. The integrated circuit is operable to drive selective deposition or activation of selected nucleotides to attach to polynucleotides in the wells to thereby generate polynucleotides representing machine-written data in the wells. The imaging assembly is operable to capture images indicative of one or more nucleotides in a polynucleotide.

Abstract: Devices, systems, and methods for non-volatile storage include a well activation device operable to modify one or more wells from a plurality of wells of a flow cell to provide a set of readable wells. Readable wells are configured to allow exposure of a well to substances from nucleotide sequencing fluids, and prevent exposure to other substances and fluids, such as nucleotide synthesizing fluids. The well activation device may also modify wells to provide a set of writeable wells. This set of wells is configured to allow exposure to the nucleotide synthesizing fluids and substances; and prevent exposure to the nucleotide sequencing fluids and substances. There may also be provisions made for risk mitigation for data errors such as generating commands to write specified data to a nucleotide sequence associated with a particular location in a storage device, reading the nucleotide sequence and performing a comparison.

Abstract: An apparatus includes a flow cell body, a plurality of electrodes, an imaging assembly, and one or more barrier features. The flow cell body defines one or more flow channels and a plurality of wells defined as recesses in the floor of each flow channel. Each well is fluidically coupled with the corresponding flow channel. The flow cell body further defines interstitial surfaces between adjacent wells. Each well defines a corresponding depth. Each electrode is positioned in a corresponding well of the plurality of wells. The electrodes are to effect writing of polynucleotides in the wells. The imaging assembly is to capture images of polynucleotides written in the wells. The one or more barrier features are positioned in the wells, between the wells, or above the wells. The one or more barrier features contain reactions in each well, reduce diffusion between the wells, or reduce optical cross-talk between the wells.

Abstract: A system writes input data to a storage device as machine-written polynucleotides; and reads machine written polynucleotides from the storage device as output data. The storage device includes a flow cell including a plurality of storage wells in which machine written polynucleotides may be stored. The storage device may include a set of electrodes corresponding to the storage wells that allow for selective interactions with wells across the surface of a flow cell. Operation of the storage device may include receiving a read request associated with a particular location in the storage device, creating a copy of a nucleotide sequence located at the particular location in the storage device, transferring the copy of the nucleotide sequence to a read location, and reading the copy of the nucleotide sequence at the read location.

Abstract: Numerous embodiments for reading or verifying a value stored in a selected memory cell in a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. In one embodiment, an input comprises a set of input bits that result in a series of input signals applied to a terminal of the selected memory cell, further resulting in a series of output signals that are digitized, shifted based on the bit location of the corresponding input bit in the set of input bits, and added to yield an output indicating a value stored in the selected memory cell.

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Optionally, compensation measures can be utilized that compensate for changes in voltage or current as the number of cells being programmed changes.