Abstract: A super junction semiconductor device includes a semiconductor portion including mesa regions protruding from a base section and spatially separated in a lateral direction parallel to a first surface of the semiconductor portion, and a compensation structure covering at least sidewalls of the mesa regions. The compensation structure includes at least two first compensation layers of a first conductivity type, at least two second compensation layers of a complementary second conductivity type, and at least one interdiffusion layer between one of the first and one of the second compensation layers.

Abstract: A super junction semiconductor device comprises a semiconductor portion with mesa regions protruding from a base section. The mesa regions are spatially separated in a lateral direction parallel to a first surface of the semiconductor portion. A compensation structure with at least two first compensation layers of a first conductivity type and at least two second compensation layers of a complementary second conductivity type may cover sidewalls of the mesa regions and portions of the base section between the mesa regions. Buried lateral faces of segments of the compensation structure may cut the first and second compensation layers between the mesa regions. A drain connection structure of the first conductivity type may extend along the buried lateral faces and may structurally connect the first compensation layers in an economic way keeping the thermal budget low.

Abstract: An active area of a semiconductor body includes a first charge-compensation structure having spaced apart n-type pillar regions, and an n-type first field-stop region of a semiconductor material in Ohmic contact with a drain metallization and the n-type pillar regions and having a doping charge per area higher than a breakdown charge per area of the semiconductor material. A punch-through area of the semiconductor body includes a p-type semiconductor region in Ohmic contact with a source metallization, a floating p-type body region and an n-type second field-stop region. The floating p-type body region extends into the active area. The second field-stop region is in Ohmic contact with the first field-stop region, forms a pn-junction with the floating p-type body region, is arranged between the p-type semiconductor region and floating p-type body region, and has a doping charge per area lower than the breakdown charge per area of the semiconductor material.

Abstract: A field-effect semiconductor device includes a semiconductor body having a first surface and an edge, an active area, and a peripheral area between the active area and the edge, a source metallization on the first surface and a drain metallization. In the active area, first conductivity type drift portions alternate with second conductivity type compensation regions. The drift portions contact the drain metallization and have a first maximum doping concentration. The compensation regions are in Ohmic contact with the source metallization. The peripheral area includes a first edge termination region and a second semiconductor region in Ohmic contact with the drift portions having a second maximum doping of the first conductivity type which lower than the first maximum doping concentration by a factor of ten. The first edge termination region of the second conductivity type adjoins the second semiconductor region and is in Ohmic contact with the source metallization.

Abstract: A semiconductor device includes a semiconductor portion with one or more impurity zones of the same conductivity type. A first electrode structure is electrically connected to the one or more impurity zones in a cell area of the semiconductor portion. At least in an edge area surrounding the cell area a recombination center density in the semiconductor portion is higher than in an active portion of the cell area.

Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Abstract: A super junction semiconductor device comprises a semiconductor portion with mesa regions protruding from a base section. The mesa regions are spatially separated in a lateral direction parallel to a first surface of the semiconductor portion. A compensation structure with at least two first compensation layers of a first conductivity type and at least two second compensation layers of a complementary second conductivity type may cover sidewalls of the mesa regions and portions of the base section between the mesa regions. Buried lateral faces of segments of the compensation structure may cut the first and second compensation layers between the mesa regions. A drain connection structure of the first conductivity type may extend along the buried lateral faces and may structurally connect the first compensation layers in an economic way keeping the thermal budget low.

Abstract: A super junction semiconductor device includes strip structures between mesa regions that protrude from a base section in a cell area. Each strip structure includes a compensation structure with a first and a second section inversely provided on opposing sides of a fill structure. Each section includes a first compensation layer of a first conductivity type and a second compensation layer of a complementary second conductivity type. The strip structures extend into an edge area surrounding the cell area. In the edge area the strip structures include end sections. The end sections may be modified to enhance break down voltage characteristics, avalanche ruggedness and commutation behavior.

Abstract: A super junction semiconductor device includes a layered compensation structure with an n-type compensation layer and a p-type compensation layer, a dielectric layer facing the p-type layer, and an intermediate layer interposed between the dielectric layer and the p-type compensation layer. The layered compensation structure and the intermediate layer are provided such that when a reverse blocking voltage is applied between the n-type and p-type compensation layers, holes accelerated in the direction of the dielectric layer have insufficient energy to be absorbed and incorporated into the dielectric material. Since the dielectric layer absorbs and incorporates significantly less holes than without the intermediate layer, the breakdown voltage remains stable over a long operation time.

Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Abstract: A semiconductor device has a source metallization, drain metallization, and semiconductor body. The semiconductor body includes a drift layer of a first conductivity contacted with the drain metallization, a buffer (and field-stop) layer of the first conductivity higher in maximum doping concentration than the drift layer, and a plurality of compensation regions of a second conductivity, each forming a pn-junction with the drift and buffer layers and in contact with the source metallization. Each compensation region includes a first portion between a second portion and the source metallization. The first portions and the drift layer form a first area having a vanishing net doping. The second portions and the buffer layer form a second area of the first conductivity. A space charge region forms in the second area when a reverse voltage of more than 30% of the device breakdown voltage is applied between the drain and source metallizations.

Abstract: A semiconductor device has a source metallization, drain metallization, and semiconductor body. The semiconductor body includes a drift layer of a first conductivity contacted with the drain metallization, a buffer (and field-stop) layer of the first conductivity higher in maximum doping concentration than the drift layer, and a plurality of compensation regions of a second conductivity, each forming a pn-junction with the drift and buffer layers and in contact with the source metallization. Each compensation region includes a first portion between a second portion and the source metallization. The first portions and the drift layer form a first area having a vanishing net doping. The second portions and the buffer layer form a second area of the first conductivity. A space charge region forms in the second area when a reverse voltage of more than 30% of the device breakdown voltage is applied between the drain and source metallizations.

Abstract: According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C.

Abstract: Disclosed is a semiconductor device including a drift region of a first doping type, a junction between the drift region and a device region, and at least one field electrode structure in the drift region. The field electrode structure includes a field electrode, a field electrode dielectric adjoining the field electrode and arranged between the field electrode and the drift region, and having an opening, at least one of a field stop region and a generation region.

Abstract: A semiconductor device includes a semiconductor body and a source metallization arranged on a first surface of the body. The body includes: a first semiconductor layer including a compensation-structure; a second semiconductor layer adjoining the first layer, comprised of semiconductor material of a first conductivity type and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; a third semiconductor layer of the first conductivity type adjoining the second layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third layer; and a fourth semiconductor layer of the first conductivity type adjoining the third layer and having a maximum doping concentration higher than that of the third layer. The first semiconductor layer is arranged between the first surface and the second semiconductor layer.

Abstract: Disclosed is a semiconductor device including a drift region of a first doping type, a junction between the drift region and a device region, and at least one field electrode structure in the drift region. The field electrode structure includes a field electrode, a field electrode dielectric adjoining the field electrode and arranged between the field electrode and the drift region, and having an opening, at least one of a field stop region and a generation region.

Abstract: A method for producing a semiconductor device with an electrode structure includes providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface, and forming a first trench extending from the first surface into the semiconductor body. The first trench is formed at least by removing the sacrificial layer in a section adjacent to the first surface. The method further includes forming a second trench by isotropically etching the semiconductor body in the first trench, forming a dielectric layer which covers sidewalls of the second trench, and forming an electrode on the dielectric layer in the second trench, the electrode and the dielectric layer in the second trench forming the electrode structure.

Abstract: A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.

Abstract: A transistor with a gate electrode structure is produced by providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface. A first trench extending from the first surface into the semiconductor body is formed by removing the sacrificial layer in a section adjacent the first surface. A second trench is formed by isotropically etching the semiconductor body in the first trench. A third trench is formed below the second trench by removing at least a part of the first sacrificial layer below the second trench. A dielectric layer is formed which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench. A gate electrode is formed on the dielectric layer in the second trench. The gate electrode and dielectric layer in the second trench form the gate electrode structure.

Abstract: A transistor with a gate electrode structure is produced by providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface. A first trench extending from the first surface into the semiconductor body is formed by removing the sacrificial layer in a section adjacent the first surface. A second trench is formed by isotropically etching the semiconductor body in the first trench. A third trench is formed below the second trench by removing at least a part of the first sacrificial layer below the second trench. A dielectric layer is formed which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench. A gate electrode is formed on the dielectric layer in the second trench. The gate electrode and dielectric layer in the second trench form the gate electrode structure.