Patents by Inventor Stefano Sivero
Stefano Sivero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130077412Abstract: Devices and circuits for row driver architectures that can improve an existing row driver circuit including a boosting capacitor and a level shifter circuit. For example, the improvement can include a decoupling inverter that decouples the level shifter from the boosting capacitor, which can reduce the time for the row driver to turn on and drive appropriate voltages to the matrix array.Type: ApplicationFiled: September 26, 2011Publication date: March 28, 2013Applicant: Elpida Memory, Inc.Inventor: Stefano Sivero
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Publication number: 20120230108Abstract: Disclosed herein is a device that comprises at least one selection/non-selection voltage receiving line, at least one word line operatively coupled to the selection/non-selection voltage receiving line, and a plurality of memory cells coupled to the word line; a selection voltage source line; and a selection voltage supply circuit comprising a first switch circuit and a first driver circuit driving the first switch circuit to be turned ON or OFF, the first switch circuit including a first node coupled to the selection voltage source line, a second node coupled to the selection/non-selection voltage receiving line of the first memory plane and a third node coupled to the selection/non-selection voltage receiving line of the second memory plane, and the first driver circuit being provided in common to the first and second memory planes.Type: ApplicationFiled: March 7, 2011Publication date: September 13, 2012Applicant: Elpida Memory, Inc.Inventors: Chiara Missiroli, Stefano Sivero, Nicola Maglione
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Patent number: 7983098Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.Type: GrantFiled: September 30, 2009Date of Patent: July 19, 2011Assignee: Atmel CorporationInventors: Marco Passerini, Stefano Sivero, Andrea Sacco, Monica Marziani
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Patent number: 7769943Abstract: A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.Type: GrantFiled: April 4, 2007Date of Patent: August 3, 2010Assignee: Atmel CorporationInventors: Stefano Surico, Stefano Sivero, Simone Bartoli, Marco Passerini
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Publication number: 20100074030Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.Type: ApplicationFiled: September 30, 2009Publication date: March 25, 2010Applicant: Atmel CorporationInventors: Marco Passerini, Stefano Sivero, Andrea Sacco, Monica Marziani
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Patent number: 7599231Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.Type: GrantFiled: October 11, 2006Date of Patent: October 6, 2009Assignee: Atmel CorporationInventors: Marco Passerini, Stefano Sivero, Andrea Sacco, Monica Marziani
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Patent number: 7579902Abstract: A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.Type: GrantFiled: December 11, 2006Date of Patent: August 25, 2009Assignee: Atmel CorporationInventors: Massimiliano Frulio, Stefano Sivero, Marco Passerini, Fabio Tassan Caser
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Patent number: 7505326Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.Type: GrantFiled: October 31, 2006Date of Patent: March 17, 2009Assignee: ATMEL CorporationInventors: Stefano Sivero, Mirella Marsella, Mauro Chinosi, Giorgio Bosisio
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Patent number: 7456678Abstract: An apparatus and method for providing a temperature compensated reference current in an electronic device is disclosed. The temperature compensated reference current is compensated for temperature and other circuit variations. The reference current is provided by an improved reference current generator and may be used in a memory device or any other desired circuit.Type: GrantFiled: October 10, 2006Date of Patent: November 25, 2008Assignee: Atmel CorporationInventors: Marco Passerini, Stefano Sivero, Mirella Marsella, Maria Mostola
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Patent number: 7436232Abstract: A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.Type: GrantFiled: September 17, 2003Date of Patent: October 14, 2008Assignee: Atmel CorporationInventors: Stefano Sivero, Massimiliano Frulio
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Publication number: 20080250191Abstract: A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.Type: ApplicationFiled: April 4, 2007Publication date: October 9, 2008Applicant: ATMEL CORPORATIONInventors: Stefano Surico, Stefano Sivero, Simone Bartoli, Marco Passerini
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Patent number: 7430150Abstract: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.Type: GrantFiled: May 5, 2005Date of Patent: September 30, 2008Assignee: Atmel CorporationInventors: Massimiliano Frulio, Stefano Sivero, Fabio Tassan Caser, Mauro Chinosi
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Patent number: 7417904Abstract: A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.Type: GrantFiled: October 31, 2006Date of Patent: August 26, 2008Assignee: ATMEL CorporationInventors: Stefano Sivero, Stefano Surico, Fabio Tassan Caser, Mauro Chinosi
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Patent number: 7414891Abstract: An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.Type: GrantFiled: January 4, 2007Date of Patent: August 19, 2008Assignee: Atmel CorporationInventors: Stefano Sivero, Marco Passerini, Fabio Tassan Caser, Simone Bartoli
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Publication number: 20080136500Abstract: A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven from the output of a last charge pump stage of the first group and an output coupled to a first voltage node. A second group of cascaded charge-pump stages is provided, the input of the first charge pump stage of the second group being driven from the output of the last charge pump stage of the first group. A second output stage has an input driven from the output of the last charge pump stage in the second group and an output coupled to a second voltage node.Type: ApplicationFiled: December 11, 2006Publication date: June 12, 2008Applicant: Atmel CorporationInventors: Massimiliano Frulio, Stefano Sivero, Marco Passerini, Fabio Tassan Caser
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Publication number: 20080101133Abstract: A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.Type: ApplicationFiled: October 31, 2006Publication date: May 1, 2008Applicant: ATMEL CORPORATIONInventors: Stefano Sivero, Stefano Surico, Fabio Tassan Caser, Mauro Chinosi
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Publication number: 20080101124Abstract: A signal generator circuit is configured to generate program signals for a memory array. The program signals are applied to word lines in the memory array, and have a transient state based on a coupling characteristic of the word lines and selector gates. The transient state is configured to minimize coupling between the word lines and the gates of the selectors so that a state of each selector remains unchanged during the transient state.Type: ApplicationFiled: October 31, 2006Publication date: May 1, 2008Applicant: ATMEL CORPORATIONInventors: Stefano Sivero, Mirella Marsella, Mauro Chinosi, Giorgio Bosisio
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Publication number: 20080089140Abstract: An apparatus and method for improving the performance of an electronic device is disclosed. An idle voltage state is introduced by an adaptive voltage generator when providing or removing a high voltage signal from a line or a node in a circuit. The idle state reduces the undesirable effects of switching disturbances caused by sudden voltage changes in a line or node.Type: ApplicationFiled: October 11, 2006Publication date: April 17, 2008Applicant: ATMEL CORPORATIONInventors: Marco Passerini, Stefano Sivero, Andrea Sacco, Monica Marziani
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Publication number: 20080084240Abstract: An apparatus and method for providing a temperature compensated reference current in an electronic device is disclosed. The temperature compensated reference current is compensated for temperature and other circuit variations. The reference current is provided by an improved reference current generator and may be used in a memory device or any other desired circuit.Type: ApplicationFiled: October 10, 2006Publication date: April 10, 2008Applicant: ATMEL CORPORATIONInventors: Marco Passerini, Stefano Sivero, Mirella Marsella, Maria Mostola
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Patent number: 7333389Abstract: An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.Type: GrantFiled: May 11, 2005Date of Patent: February 19, 2008Assignee: Atmel CorporationInventors: Stefano Sivero, Simone Bartoli, Fabio Tassan Caser, Riccardo Riva Reggiori