Patents by Inventor Stefano Sivero
Stefano Sivero has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7176750Abstract: A fast power-on band-gap reference circuit includes a buffer, a first band-gap logic, and a second high drive band-gap logic. During power-on of the band-gap reference circuit, both the first band-gap logic and the second high drive band-gap logic are activated, in which the first band-gap logic charges an output of the first band-gap logic and the second high drive band-gap logic charges a capacitance associated with an output of the band-gap reference circuit. When the output of the first band-gap logic reaches a predetermined value, the second high drive band-gap logic is deactivated and the output of the first band-gap logic is couple to the output of the band-gap reference circuit through the buffer.Type: GrantFiled: May 9, 2005Date of Patent: February 13, 2007Assignee: Atmel CorporationInventors: Giorgio Oddone, Stefano Sivero, Giorgio Bosisio, Andrea Bettini
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Patent number: 7049880Abstract: A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.Type: GrantFiled: May 2, 2005Date of Patent: May 23, 2006Assignee: Atmel CorporationInventors: Stefano Sivero, Lorenzo Bedarida, Massimiliano Frulio
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Publication number: 20060083097Abstract: A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.Type: ApplicationFiled: May 5, 2005Publication date: April 20, 2006Inventors: Massimiliano Frulio, Stefano Sivero, Fabio Tassan Caser, Mauro Chinosi
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Publication number: 20060077746Abstract: An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.Type: ApplicationFiled: May 11, 2005Publication date: April 13, 2006Inventors: Stefano Sivero, Simone Bartoli, Fabio Tassan Caser, Riccardo Reggiori
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Publication number: 20060038609Abstract: A fast power-on band-gap reference circuit includes a band-gap logic and a band-gap dummy logic. During power-on, both the band-gap logic and the band-gap dummy logic are activated and charges the capacitance of a band-gap line. When an output of the band-gap logic reaches a predetermined value, the band-gap dummy logic is deactivated. Thus, the band-gap dummy logic, with a high drive capability, charges the band-gap capacitance at the same time the band-gap logic starts to generate the compensate temperature voltage. In this manner, the band-gap reference circuit reaches its stable, functional state faster than conventional circuits, in the range of a few microseconds.Type: ApplicationFiled: May 9, 2005Publication date: February 23, 2006Inventors: Giorgio Oddone, Stefano Sivero, Giorgio Bosisio, Andrea Bettini
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Publication number: 20050189983Abstract: A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.Type: ApplicationFiled: May 2, 2005Publication date: September 1, 2005Inventors: Stefano Sivero, Lorenzo Bedarida, Massimiliano Frulio
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Patent number: 6906576Abstract: A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.Type: GrantFiled: January 7, 2004Date of Patent: June 14, 2005Assignee: Atmel CorporationInventors: Stefano Sivero, Lorenzo Bedarida, Massimiliano Frulio
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Publication number: 20050073355Abstract: A regulated charge pump circuit having two-way switching means that switches between a first feedback pathway that provides a precise and stable voltage output and a second feedback pathway that provides a regulated voltage output with low current consumption from the power source. The first feedback pathway maintains a precise voltage output by regulating a pass device that draws current to the voltage output. The second feedback pathway regulates the voltage output by controlling the connection of a clock input to the charge pump. A variable resistor is used to set the regulated level of the voltage output. A digital-to analog converter is formed by using a combination logic circuit to convert a digital input signal to a control signal for the variable resistor.Type: ApplicationFiled: January 7, 2004Publication date: April 7, 2005Inventors: Stefano Sivero, Lorenzo Bedarida, Massimiliano Frulio
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Publication number: 20040257131Abstract: A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.Type: ApplicationFiled: September 17, 2003Publication date: December 23, 2004Inventors: Stefano Sivero, Massimiliano Frulio
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Patent number: 6828834Abstract: A power-on management system for an on-chip voltage down-converter, monitoring both external and internal voltage supplies to independently determine when both supplies have reached minimum levels for proper operation of on-chip circuitry. The power-on management system supplies output signals that: control the discharge of the internal supply nodes at the initiation of power-on; force the active mode of the voltage down-converter; and deactivate a fast local voltage reference on completion of power-on.Type: GrantFiled: December 24, 2002Date of Patent: December 7, 2004Assignee: Atmel CorporationInventors: Stefano Sivero, Riccardo Riva-Reggiori, Lorenzo Bedarida
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Patent number: 6794927Abstract: An voltage regulation apparatus for generating a supply voltage internally within an integrated circuit with a modular arrangement of charge pumps. The charge pumps feature a first plurality of parallel-connected blocks of charge pump stages including a first block of charge pump stages, a last block of charge pump stages, and at least one intermediate block of charge pump stages therebetween. Each of the parallel-connected blocks of charge pump stages includes a group of a second plurality of charge pump stages cascade-connected in series; and an output stage connected to an output node. Desired output voltages are obtained by using combinatorial clock signals, generated by a logic circuit, directed to the various charge pump stages.Type: GrantFiled: December 24, 2002Date of Patent: September 21, 2004Assignee: Atmel CorporationInventors: Lorenzo Bedarida, Stefano Sivero, Davide Manfre
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Patent number: 6785183Abstract: A voltage down-converter system, with a stand-by mode and an active mode, for a memory device with the following components. A charge node is configured to receive a charge. A first transistor has a first gate and the first transistor is configured to supply a load current to the memory device. A first switch is coupled to the charge node and the first gate, the first switch being configured to apply the charge in the charge node to the first gate during transition from stand-by to active modes. A second transistor is coupled to the first gate and configured to bias the first transistor to an inactive state during stand-by mode. A second switch is coupled to the first gate and the second transistor, the second switch being configured to apply a voltage difference at the second transistor to the first gate during the stand-by mode.Type: GrantFiled: April 3, 2003Date of Patent: August 31, 2004Assignee: Atmel CorporationInventors: Stefano Sivero, Riccardo Riva Reggiori, Fabio Tassan Caser
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Patent number: 6771200Abstract: A DAC-based voltage regulator system for a non-volatile memory device comprises a charge pump circuit having an enable input and a voltage output node. A voltage-to-current converter has an input coupled to the voltage output node and an output coupled to a virtual ground node. A current source is coupled to the virtual ground node and sinks one of a plurality of currents in response to states of a plurality of digital input signals. A transconductance amplifier has an inverting input at the virtual ground node, a non-inverting input coupled to a reference voltage potential, and an output. A comparator has a first input coupled to the output of the transconductance amplifier, a second input coupled to a reference voltage potential, and an output coupled to the enable input of said charge pump.Type: GrantFiled: April 3, 2003Date of Patent: August 3, 2004Assignee: Atmel CorporationInventors: Massimiliano Frulio, Stefano Sivero, Simone Bartozi, Sabina Mognoni
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Patent number: 6734701Abstract: An output buffer switch-on control circuit includes several transistors and a discharge current control circuit. A first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. A second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. A third transistor is controlled by the output data source and has a first terminal connected to a common voltage. A fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor. The fourth transistor also has a second terminal connected to the common voltage. The discharge current control circuit is preferably actively-controlled and is connected between a second terminal of the first transistor and a second terminal of the third transistor.Type: GrantFiled: December 18, 2002Date of Patent: May 11, 2004Assignee: Atmel CorporationInventors: Lorenzo Bedarida, Stefano Sivero, Davide Manfre
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Publication number: 20040080360Abstract: A variable charge pump circuit uses a plurality of selectable loads to minimize the voltage ripples of the pumped output by selecting the appropriate load for a preselected pump voltage. The charge pump circuit also compares the pump voltage to a reference voltage to shut down the variable charge pump circuit if the pump voltage is larger than the reference voltage. The charge pump circuit also compares the maximum voltage output to the reference voltage to monitor whether the maximum ripple on voltage output is larger than the reference voltage. The charge pump circuit comprises one or more stages operable to receive a supply voltage and generate one or more pump voltages, a plurality of loads each associated with a specific pump voltage, and a load selector means coupled to the output pump and the plurality of loads for selecting a load associated with a specific pump voltage.Type: ApplicationFiled: January 27, 2003Publication date: April 29, 2004Inventors: Lorenzo Bedarida, Simone Bartoli, Stefano Sivero
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Patent number: 6724241Abstract: A variable charge pump circuit uses a plurality of selectable loads to minimize the voltage ripples of the pumped output by selecting the appropriate load for a preselected pump voltage. The charge pump circuit also compares the pump voltage to a reference voltage to shut down the variable charge pump circuit if the pump voltage is larger than the reference voltage. The charge pump circuit also compares the maximum voltage output to the reference voltage to monitor whether the maximum ripple on voltage output is larger than the reference voltage. The charge pump circuit comprises one or more stages operable to receive a supply voltage and generate one or more pump voltages, a plurality of loads each associated with a specific pump voltage, and a load selector means coupled to the output pump and the plurality of loads for selecting a load associated with a specific pump voltage.Type: GrantFiled: January 27, 2003Date of Patent: April 20, 2004Assignee: Atmel CorporationInventors: Lorenzo Bedarida, Simone Bartoli, Stefano Sivero
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Publication number: 20040051554Abstract: An output buffer switch-on control circuit includes several transistors and a discharge current control circuit. A first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. A second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. A third transistor is controlled by the output data source and has a first terminal connected to a common voltage. A fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor. The fourth transistor also has a second terminal connected to the common voltage. The discharge current control circuit is preferably actively-controlled and is connected between a second terminal of the first transistor and a second terminal of the third transistor.Type: ApplicationFiled: December 18, 2002Publication date: March 18, 2004Inventors: Lorenzo Bedarida, Stefano Sivero, Davide Manfre
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Publication number: 20040052145Abstract: A voltage down-converter system, with a stand-by mode and an active mode, for a memory device with the following components. A charge node is configured to receive a charge. A first transistor has a first gate and the first transistor is configured to supply a load current to the memory device. A first switch is coupled to the charge node and the first gate, the first switch being configured to apply the charge in the charge node to the first gate during transition from stand-by to active modes. A second transistor is coupled to the first gate and configured to bias the first transistor to an inactive state during stand-by mode. A second switch is coupled to the first gate and the second transistor, the second switch being configured to apply a voltage difference at the second transistor to the first gate during the stand-by mode.Type: ApplicationFiled: April 3, 2003Publication date: March 18, 2004Applicant: Atmel CorporationInventors: Stefano Sivero, Riccardo Riva Reggiori, Fabio Tassan Caser
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Publication number: 20040046603Abstract: An voltage regulation apparatus for generating a supply voltage internally within an integrated circuit with a modular arrangement of charge pumps. The charge pumps feature a first plurality of parallel-connected blocks of charge pump stages including a first block of charge pump stages, a last block of charge pump stages, and at least one intermediate block of charge pump stages therebetween. Each of the parallel-connected blocks of charge pump stages includes a group of a second plurality of charge pump stages cascade-connected in series; and an output stage connected to an output node. Desired output voltages are obtained by using combinatorial clock signals, generated by a logic circuit, directed to the various charge pump stages.Type: ApplicationFiled: December 24, 2002Publication date: March 11, 2004Inventors: Lorenzo Bedarida, Stefano Sivero, Davide Manfre
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Publication number: 20040046681Abstract: A DAC-based voltage regulator system for a non-volatile memory device comprises a charge pump circuit having an enable input and a voltage output node. A voltage-to-current converter has an input coupled to the voltage output node and an output coupled to a virtual ground node. A current source is coupled to the virtual ground node and sinks one of a plurality of currents in response to states of a plurality of digital input signals. A transconductance amplifier has an inverting input at the virtual ground node, a non-inverting input coupled to a reference voltage potential, and an output. A comparator has a first input coupled to the output of the transconductance amplifier, a second input coupled to a reference voltage potential, and an output coupled to the enable input of said charge pump.Type: ApplicationFiled: April 3, 2003Publication date: March 11, 2004Applicant: Atmel CorporationInventors: Massimiliano Frulio, Stefano Sivero, Simone Bartoli, Sabina Mognoni