Patents by Inventor Stephan Grunow
Stephan Grunow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10229875Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: GrantFiled: March 17, 2016Date of Patent: March 12, 2019Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 9893011Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.Type: GrantFiled: October 1, 2015Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Dan Moy, Andrew H. Simon
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Patent number: 9685404Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.Type: GrantFiled: January 11, 2012Date of Patent: June 20, 2017Assignee: International Business Machines CorporationInventors: Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald Filippi, Stephan Grunow, Naftali E. Lustig, Dan Moy, Andrew H. Simon
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Patent number: 9425144Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.Type: GrantFiled: December 23, 2014Date of Patent: August 23, 2016Assignee: GlobalFoundries, Inc.Inventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali Lustig, Andrew H. Simon, Junjing Bao
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Publication number: 20160197039Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: ApplicationFiled: March 17, 2016Publication date: July 7, 2016Inventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 9360525Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: GrantFiled: February 25, 2014Date of Patent: June 7, 2016Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Publication number: 20160027733Abstract: A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.Type: ApplicationFiled: October 1, 2015Publication date: January 28, 2016Inventors: Junjing Bao, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Dan Moy, Andrew H. Simon
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Patent number: 9142506Abstract: E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.Type: GrantFiled: November 13, 2013Date of Patent: September 22, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20150235946Abstract: A metal fuse structure using redundant vias. The redundant vias are formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes: a first dielectric layer having a metal feature; a second dielectric layer having a first metal connector embedded therein; and a third dielectric layer having a second metal connector embedded therein. The metal connectors include at least one via and one line, and at least one metal connector has at least two vias.Type: ApplicationFiled: May 4, 2015Publication date: August 20, 2015Inventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon
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Patent number: 9093164Abstract: A metal fuse structure using redundant vias formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes a first dielectric layer having a conductor, a second dielectric layer above the first dielectric layer having a first conductive line and a first via, the first via is on the conductor, the first conductive line is on the first via, the first via is the only electrical connection between the first conductive line and the conductor, and a third dielectric layer above the second dielectric layer having a second conductive line, a second via and a third via, the second via and the third via are both on the first conductive line, the second conductive line is on both the first via and the second via.Type: GrantFiled: November 17, 2011Date of Patent: July 28, 2015Assignee: International Business Machines CorporationInventors: Ronald G. Filippi, Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon
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Patent number: 9059169Abstract: E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.Type: GrantFiled: June 21, 2011Date of Patent: June 16, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon
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Publication number: 20150137312Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.Type: ApplicationFiled: December 23, 2014Publication date: May 21, 2015Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali Lustig, Andrew H. Simon, Junjing Bao
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Patent number: 8962467Abstract: Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.Type: GrantFiled: February 17, 2012Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Samuel S. Choi, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Junjing Bao
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Patent number: 8836124Abstract: A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.Type: GrantFiled: March 8, 2012Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Samuel Sung Shik Choi, Ronald G. Filippi, Stephan Grunow, Naftali Eliahu Lustig, Andrew H. Simon
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Publication number: 20140167772Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: ApplicationFiled: February 25, 2014Publication date: June 19, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 8742766Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: GrantFiled: September 30, 2013Date of Patent: June 3, 2014Assignee: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Publication number: 20140070362Abstract: E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.Type: ApplicationFiled: November 13, 2013Publication date: March 13, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Griselda BONILLA, Kaushik CHANDA, Samuel S. CHOI, Ronald G. FILIPPI, Stephan GRUNOW, Naftali E. LUSTIG, Andrew H. SIMON
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Publication number: 20140028325Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Ronald G. Filippi, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Patent number: 8633707Abstract: A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.Type: GrantFiled: March 29, 2011Date of Patent: January 21, 2014Assignee: International Business Machines CorporationInventors: Ronald G. Filippi, Griselda Bonilla, Kaushik Chanda, Stephan Grunow, Naftali E. Lustig, Andrew H. Simon, Ping-Chuan Wang
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Publication number: 20130234284Abstract: A fuse structure includes within an aperture within a dielectric layer located over a substrate that exposes a conductor contact layer within the substrate a seed layer interposed between the conductor contact layer and another conductor layer. The seed layer includes a doped copper material that includes a dopant immobilized predominantly within the seed layer. The fuse structure may be severed while not severing a conductor interconnect structure also located over the substrate that exposes a second conductor contact layer within a second aperture. In contrast with the fuse structure that includes the doped seed layer having the immobilized dopant, the interconnect structure includes a doped seed layer having a mobile dopant.Type: ApplicationFiled: March 8, 2012Publication date: September 12, 2013Applicant: International Business Machines CorporationInventors: Griselda Bonilla, Kaushik Chanda, Samuel Sung Shik Choi, Ronald G. Filippi, Stephan Grunow, Naftali Eliahu Lustig, Andrew H. Simon