Abstract: The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).

Abstract: The present invention provides a method for forming an interconnect on a semiconductor substrate 100. The method includes forming an opening 230 over an inner surface of the opening 130, the depositing forming a reentrant profile near a top portion of the opening 130. A portion of barrier 230 is etched, which removes at least a portion of the barrier 230 to reduce the reentrant profile. The etching also removes at least a portion of the barrier 230 layer at the bottom of the opening 130.

Abstract: A method for fabricating a seed layer. A seed layer (126) is deposited over a barrier layer (124) using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower/zero AC bias power step. The low AC bias power step provides low overhang. The high AC bias power step provides good sidewall coverage. The lower/zero AC bias step recovers areas exposed by re-sputtering during the high AC bias power step.

Abstract: A method of fabricating a semiconductor device is provided. An interlayer dielectric layer is formed on one or more semiconductor layers (402). One or more feature regions are formed in the interlayer dielectric layer (404). A first conductive layer is formed in at least a portion of the feature regions and on the interlayer dielectric layer (406)). A first anneal is performed that promotes grain growth of the first conductive layer (408). An additional conductive layer is formed on the first conductive layer (410) and an additional anneal is performed (412) that promotes grain growth of the additional conductive layer and further promotes grain size growth of the first conductive layer. Additional conductive layers can be formed and annealed until a sufficient overburden amount has been obtained. Subsequently, a planarization process is performed that removes excess conductive material and thereby forms and isolates conductive features in the semiconductor device (414).

Abstract: A method for fabricating a barrier layer. A first barrier layer (124) is deposited over a dielectric (104) including in a trench (108) and via (106). A re-sputtering process is then performed to remove said first barrier layer (124) from a bottom of the via (106) without substantially reducing a thickness of said first barrier layer (124) at a bottom of the trench (108) using an intermediate DC target power. A second barrier layer (126) is then deposited.

Abstract: A method for fabricating a seed layer. A seed layer (126) is deposited over a barrier layer (124) using a three-step process comprising a low AC bias power step, a high AC bias power step, and a lower/zero AC bias power step. The low AC bias power step provides low overhang. The high AC bias power step provides good sidewall coverage. The lower/zero AC bias step recovers areas exposed by re-sputtering during the high AC bias power step.

Abstract: A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138).

Abstract: An integrated circuit copper interconnect structure is formed by forming a dielectric layer (90) over a semiconductor substrate (10). Trenches (110) and vias (120) are formed in the dielectric layer (90) and a barrier layer (130) is formed in the trenches (110) and vias (120) using material such as iridium, iridium oxide, ruthenium, ruthenium oxide, rhodium, rhodium oxide, rhenium, rhenium oxide, platinum, platinum oxide, palladium and palladium oxide. Copper (147) is then used to fill the remaining area in the trenches (110) and vias (120).

Abstract: An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.

Abstract: A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).

Abstract: A stacked interconnect structure to connect a first layer copper line with a second layer copper line and method of making the same includes depositing a barrier layer over the inner surfaces of a via extending through a first dielectric layer between the first and second layer copper lines. The first barrier layer provides a barrier to copper diffusion into the dielectric layer. The first barrier layer is then selectively etched from the bottom surface of the via, after which a second barrier layer is deposited over the vertical and bottom surfaces of the via. The second barrier layer also provides a barrier to the diffusion of copper, but is less resistive than the first barrier, and ensure wettability of the copper.

Abstract: A Low K dielectric layer (20) is formed over a semiconductor (10). Trenches (110, 120) are formed in the dielectric layer (2) and a barrier layer (70) is formed in the trenches. The barrier layer has a thickness of X1 over the upper surface of the dielectric layer and X2 on the sidewalls of the trenches where X1 is greater than X2. A second barrier layer (130) can be formed over the first barrier layer (70) and copper (100) is formed over both barrier layers to fill the trench.

Abstract: A coil (50) is placed adjacent to a semiconductor wafer (10). An AC excitation current is used to create a changing electromagnetic field (60) is the wafer (10). The wafer is heated by a heat source (20) and the conductivity of the wafer (10) will change as a function of the wafer temperature. Induced eddy currents will cause the inductance of the coil (50) to change and the temperature of the wafer (10) can be determined by monitoring the inductance of the coil (50).

Abstract: A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).

Abstract: A method for forming improved diffusion barriers for copper lines in integrated circuits is described. A low-k dielectric layer (10) is formed over a semiconductor (5). A trench (15) is formed in the low-k dielectric layer (10) and a TiNSi layer (20) is formed in the trench. An ?-Ta layer (30) is formed over the TiNSi layer (20) and copper (40) is subsequently formed in the trench (15) filling the trench (15).