Abstract: An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative return address buffer and a committed return address buffer, both of which having multiple entries that may include predicted return addresses that have been pushed onto the return buffer.

Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Abstract: Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.

Abstract: Toggling between accessing an entry in a global history with a stew created from branch predictions implied by the ordering of instructions within a trace of a trace cache when a trace is read out of a trace cache, and accessing an entry in a global history with repeatable variations of a stew when there is more than branch instruction within a trace within the trace cache and at least a second branch instruction is read out.

Abstract: A computer architecture to process load instructions by allowing multiple mappings between logical registers and the same physical register is disclosed. The computer architecture includes a processor having a physical registers. The processor also includes a decoder to decode a load instruction that names a destination logical register. The processor also includes a register allocation table to map the destination logical register to a physical register within the plurality of physical registers. If the load instruction is predicted to collide with a prior load instruction that names a destination logical register, then the register allocation table maps the destination logical register to the physical register allocated to the first load instruction.

Abstract: A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

Abstract: Apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.

Abstract: Embodiments of the present invention provide a pre-decoder in a front-end system provided between an instruction cache and a decoder. The front-end system may toggle between two modes of operation. In a first mode, called the “fast mode” the front-end system retrieves pre-decoded instructions from the instruction cache and decodes them directly. In a second mode, called the “marking mode,” the front-end system retrieves data from the instruction cache and synchronizes to them prior to decoding. Synchronization results may be stored back in the instruction cache for later use.

Abstract: A stack pointer update technique in which the stack pointer is updated without executing micro-operations to add or subtract a stack pointer value. The stack pointer update technique is also described to reset the stack pointer to a predetermined value without executing micro-operations to add or subtract stack a stack pointer value.

Abstract: A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of cache banks is associated with the instruction.

Abstract: A computer architecture to process load instructions by allowing multiple mappings between logical registers and the same physical register is disclosed. The computer architecture includes a processor having a physical registers. The processor also includes a decoder to decode a load instruction that names a destination logical register. The processor also includes a register allocation table to map the destination logical register to a physical register within the plurality of physical registers. If the load instruction is predicted to collide with a prior load instruction that names a destination logical register, then the register allocation table maps the destination logical register to the physical register allocated to the first load instruction.

Abstract: Apparatus and methods to filter memory record updates. A microprocessor can include a memory record update filter. The memory record update filter can include a table memory populated by a plurality of data entries. Each data entry can include a data tag field to store a data tag, a data field to store a data value, and a filter field to store a filter value. A first comparator can be in communication with the data tag field of the table memory and a data accessing information input to perform a data tag comparison. A second comparator can be in communication with the filter field of the table memory and a data value input. A control circuit can be in communication with the table memory, the first comparator, and the second comparator.

Abstract: A method and apparatus for identifying virtual addresses in a cache line. To differentiate candidate virtual addresses from data values and random bit patterns, the upper bits of an address-sized word in the cache line are compared with the upper bits of the cache line's effective address. If the upper bits of the address-sized word match the upper bits of the effective address, the address-sized word is identified as a candidate virtual address.

Abstract: A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address.

Abstract: Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.

Abstract: Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimized cost and performance.

Abstract: In a processing core, a newly received load instruction may be dependent upon a previously received store instruction. The core may include a predictor to predict such dependencies and provide an identification of a colliding store instruction. The load instruction may be stored in a scheduler with a dependency marker. Thereafter, the load instruction may be prevented from executing until after execution of the colliding store. Upon execution of the load, the accuracy of the prediction is confirmed. Upon retirement of the load instruction, new prediction results may be provided to the predictor.

Abstract: A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single clock cycle. The cache architecture may find application in a front end processing system of a processor storing instruction segments. If a first instruction segment does not occupy the full width of the cache, other instruction segments can be retrieved from the cache simultaneously with the first instruction segment. The cache may be organized into a plurality of cache banks, each cache bank being independently addressed. Each bank may consist of several cache ways.

Abstract: The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

Abstract: Apparatus and methods to filter memory record updates. A microprocessor can include a memory record update filter. The memory record update filter can include a table memory populated by a plurality of data entries. Each data entry can include a data tag field to store a data tag, a data field to store a data value, and a filter field to store a filter value. A first comparator can be in communication with the data tag field of the table memory and a data accessing information input to perform a data tag comparison. A second comparator can be in communication with the filter field of the table memory and a data value input. A control circuit can be in communication with the table memory, the first comparator, and the second comparator.