Abstract: In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated-in a processor core.

Abstract: A computer architecture to process move instructions by allowing multiple mappings between logical registers and the same physical register. In one embodiment, a counter is associated with each physical register to indicate when the physical register is free. A register-to-register move instruction is processed by mapping the logical destination register of the move instruction to the same physical register to which the logical source register of the move instruction is mapped. An immediate-to-register move instruction is processed by mapping the logical destination register of the move instruction to a physical register storing the immediate.

Abstract: A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single clock cycle. The cache architecture may find application in a front end processing system of a processor storing instruction segments. If a first instruction segment does not occupy the full width of the cache, other instruction segments can be retrieved from the cache simultaneously with the first instruction segment. The cache may be organized into a plurality of cache banks, each cache bank being independently addressed. Each bank may consist of several cache ways.

Abstract: Embodiments of the present invention provide a pre-decoder in a front-end system provided between an instruction cache and a decoder. The front-end system may toggle between two modes of operation. In a first mode, called the “fast mode” the front-end system retrieves pre-decoded instructions from the instruction cache and decodes them directly. In a second mode, called the “marking mode,” the front-end system retrieves data from the instruction cache and synchronizes to them prior to decoding. Synchronization results may be stored back in the instruction cache for later use.

Abstract: A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.

Abstract: A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address.

Abstract: An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative return address buffer and a committed return address buffer, both of which having multiple entries that may include predicted return addresses that have been pushed onto the return buffer.

Abstract: A content prefetcher having a prefetch chain reinforcement mechanism. In response to a prefetch hit at a cache line within a prefetch chain, a request depth of the hit cache line is promoted and the hit cache line is scanned for candidate virtual addresses in order to reinforce the prefetch chain.

Abstract: A method and apparatus for issuing one or more next-line prefetch requests from a predicted memory address. The first issued next-line prefetch request corresponds to a cache line having a memory address contiguous with the predicted memory address. Any subsequent next-line prefetch request corresponds to a cache line having a memory address contiguous with a memory address associated with a preceding next-line prefetch request.

Abstract: A method and apparatus for identifying virtual addresses in a cache line. To differentiate candidate virtual addresses from data values and random bit patterns, the upper bits of an address-sized word in the cache line are compared with the upper bits of the cache line's effective address. If the upper bits of the address-sized word match the upper bits of the effective address, the address-sized word is identified as a candidate virtual address.

Abstract: A content prefetcher including a virtual address predictor. The virtual address predictor identifies candidate virtual addresses in a cache line without reference to an external address source.

Abstract: Embodiments of the present invention provide a pre-decoder in a front-end system provided between an instruction cache and a decoder. The front-end system may toggle between two modes of operation. In a first mode, called the “fast mode” the front-end system retrieves pre-decoded instructions from the instruction cache and decodes them directly. In a second mode, called the “marking mode,” the front-end system retrieves data from the instruction cache and synchronizes to them prior to decoding. Synchronization results may be stored back in the instruction cache for later use.

Abstract: A system and method for storing only one copy of a data block that is shared by two or more processes is described. In one embodiment, a global/non-global predictor predicts whether a data block, specified by a linear address, is shared or not shared by two or more processes. If the data block is predicted to be non-shared, then a portion of the linear address referencing the data block is combined with a process identifier that is unique to form a global/non-global linear address. If the data block is predicted to be shared, then the global/non-global linear address is the linear address itself. If the prediction as to whether or not the data block is shared is incorrect, then the actual value of whether or not the data block is shared is used in computing a corrected global/non-global linear address.

Abstract: In an enhanced virtual renaming scheme within a processor, multiple logical registers may be mapped to a single physical register. A value cache determines whether a new value generated pursuant to program instructions matches values associated with previously executed instructions. If so, the logical register associated with the newly executed instruction shares the physical register. Also, deadlock preventatives measures may be integrated into a register allocation unit in a manner that “steals” a physical register from a younger executed instruction when a value from an older instruction is generated in a processor core.

Abstract: Apparatus and methods to filter memory record updates. A microprocessor can include a memory record update filter. The memory record update filter can include a table memory populated by a plurality of data entries. Each data entry can include a data tag field to store a data tag, a data field to store a data value, and a filter field to store a filter value. A first comparator can be in communication with the data tag field of the table memory and a data accessing information input to perform a data tag comparison. A second comparator can be in communication with the filter field of the table memory and a data value input. A control circuit can be in communication with the table memory, the first comparator, and the second comparator.

Abstract: A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single clock cycle. The cache architecture may find application in a front end processing system of a processor storing instruction segments. If a first instruction segment does not occupy the full width of the cache, other instruction segments can be retrieved from the cache simultaneously with the first instruction segment. The cache may be organized into a plurality of cache banks, each cache bank being independently addressed. Each bank may consist of several cache ways.

Abstract: In a scheduler, dependencies between newly received load microinstructions and older store microinstructions are predicted. If a dependency is predicted, the load microinstruction is stored in the scheduler with a marker to indicate that scheduling of the load microinstruction is to be deferred. The marker may be cleared when the colliding store, the store that caused the dependency, has executed.

Abstract: A hybrid branch predictor is disclosed. The predictor includes prediction aiding information, a plurality of branch predictors to provide a plurality of branch predictions, a plurality of storage elements to hold less than full extent of the branch predictions, but sharing information among said plurality of storage elements enables extraction of said full extent of the prediction. The predictor also includes a selection mechanism to select a prediction from the plurality of branch predictions.

Abstract: The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provides potentially valuable insight into data values. Upon encountering a branch if equal instruction and this instruction is predicted as taken or a branch if not equal instruction and this instruction is predicted as not taken, this invention assumes that the two operands used to determine the conditional branch are equal. The data predictions are safe because a data misprediction means a conditional branch misprediction which results in a pipeline flush of the instructions following the conditional branch instruction including the data mispredictions.

Abstract: A processor architecture for providing many-to-one mappings between logical registers and physical registers, so that more than one logical register may map to the same physical register. Each physical register has an associated counter to indicate whether the physical register is free. A counter is incremented each time a mapping is made to its associated physical register, and is decremented when that mapping is no longer needed. If a logical register named in a decoded instruction is predicted to have the same value as a value stored in a physical register, then the logical register is mapped to the physical register.