Patents by Inventor Stephan Lutgen

Stephan Lutgen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10483430
    Abstract: A emitting diode (LED) includes an epitaxial structure defining a base and a mesa on the base. The base defines a light emitting surface of the LED and includes current spreading layer. The mesa includes a thick confinement layer, a light generation area on the thick confinement layer to emit light, a thin confinement layer on the light generation area, and a contact layer on the thin confinement layer, the contact layer defining a top of the mesa. A reflective contact is on the contact layer to reflect a portion of the light emitted from the light generation area, the reflected light being collimated at the mesa and directed through the base to the light emitting surface. In some embodiments, the epitaxial structure grown on a non-transparent substrate. The substrate is removed, or used to form an extended reflector to collimate light.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: November 19, 2019
    Assignee: Facebook Technologies, LLC
    Inventors: Stephan Lutgen, David Massoubre
  • Publication number: 20190341521
    Abstract: A emitting diode (LED) includes an epitaxial structure defining a base and a mesa on the base. The base defines a light emitting surface of the LED and includes current spreading layer. The mesa includes a thick confinement layer, a light generation area on the thick confinement layer to emit light, a thin confinement layer on the light generation area, and a contact layer on the thin confinement layer, the contact layer defining a top of the mesa. A reflective contact is on the contact layer to reflect a portion of the light emitted from the light generation area, the reflected light being collimated at the mesa and directed through the base to the light emitting surface. In some embodiments, the epitaxial structure grown on a non-transparent substrate. The substrate is removed, or used to form an extended reflector to collimate light.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Inventors: Stephan Lutgen, David Massoubre
  • Patent number: 10468552
    Abstract: Disclosed herein are light emitting diodes (LEDs) having a high efficiency. A light emitting diode including an active light emitting layer within a semiconductor layer is provided. The semiconductor layer has a mesa shape. The light emitting diode also includes a substrate having a first surface on which the semiconductor layer is positioned and an outcoupling surface opposite to the first surface. Light generated by the active light emitting layer is incident on the outcoupling surface and propagates toward an optical element downstream of the outcoupling surface. The light emitting diode also includes a first anti-reflection coating adjacent to the outcoupling surface; an index-matched material between the outcoupling surface and the optical element, wherein an index of refraction of the index-matched material is greater than or equal to an index of refraction of the optical element; and/or secondary optics adjacent to the outcoupling surface.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: November 5, 2019
    Assignee: Facebook Technologies, LLC
    Inventor: Stephan Lutgen
  • Publication number: 20190305188
    Abstract: Disclosed herein are systems and methods for reducing surface recombination losses in micro-LEDs. In some embodiments, an LED includes a semiconductor layer including an active light emitting layer. A light outcoupling surface of the semiconductor layer has a diameter that is less than two times an electron diffusion length of a material of the semiconductor layer. The LED also includes a passivation layer that is formed on an outer surface of the semiconductor layer opposite to the light outcoupling surface. The passivation layer includes a dielectric material, and the passivation layer is in direct contact with a portion of the active light emitting layer.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Inventors: Thomas Lauermann, Stephan Lutgen, David Hwang
  • Publication number: 20190305183
    Abstract: Disclosed herein are light emitting diodes (LEDs) having a high efficiency. A light emitting diode including an active light emitting layer within a semiconductor layer is provided. The semiconductor layer has a mesa shape. The light emitting diode also includes a substrate having a first surface on which the semiconductor layer is positioned and an outcoupling surface opposite to the first surface. Light generated by the active light emitting layer is incident on the outcoupling surface and propagates toward an optical element downstream of the outcoupling surface. The light emitting diode also includes a first anti-reflection coating adjacent to the outcoupling surface; an index-matched material between the outcoupling surface and the optical element, wherein an index of refraction of the index-matched material is greater than or equal to an index of refraction of the optical element; and/or secondary optics adjacent to the outcoupling surface.
    Type: Application
    Filed: May 2, 2018
    Publication date: October 3, 2019
    Inventor: Stephan Lutgen
  • Publication number: 20190305181
    Abstract: Disclosed herein are systems and methods for reducing surface recombination losses in micro-LEDs. In some embodiments, a method includes reducing a lateral carrier diffusion in an outer region of a semiconductor layer by implanting ions in the outer region of the semiconductor layer. The semiconductor layer includes an active light emitting layer. An outcoupling surface of the semiconductor layer has a diameter of less than 10 ?m. The outer region of the semiconductor layer extends from an outer surface of the semiconductor layer to a central region of the semiconductor layer that is shaded by a mask during the implanting of the ions.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Inventors: Thomas Lauermann, Stephan Lutgen, David Hwang
  • Publication number: 20190305185
    Abstract: Disclosed herein are systems and methods for reducing surface recombination losses in micro-LEDs. In some embodiments, a method includes increasing a bandgap in an outer region of a semiconductor layer by implanting ions in the outer region of the semiconductor layer and subsequently annealing the outer region of the semiconductor layer to intermix the ions with atoms within the outer region of the semiconductor layer. The semiconductor layer includes an active light emitting layer. A light outcoupling surface of the semiconductor layer has a diameter of less than 10 ?m. The outer region of the semiconductor layer extends from an outer surface of the semiconductor layer to a central region of the semiconductor layer that is shaded by a mask during the implanting of the ions.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Inventors: Thomas Lauermann, Stephan Lutgen, David Hwang
  • Publication number: 20190097032
    Abstract: A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 28, 2019
    Applicant: AZURSPACE Solar Power GmbH
    Inventors: Stephan LUTGEN, Saad MURAD
  • Patent number: 10211296
    Abstract: An epitaxial group-III-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-III-nitride layers, wherein the interlayer structure comprises a group-III-nitride interlayer material having a larger band gap than the materials of the first and second group-III-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-III-nitride layers.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: February 19, 2019
    Assignee: AzurSpace Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
  • Publication number: 20180331187
    Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 15, 2018
    Applicant: AZURSPACE Solar Power GmbH
    Inventors: Stephan LUTGEN, Saad MURAD, Ashay CHITNIS
  • Patent number: 10128362
    Abstract: A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 13, 2018
    Assignee: AZURSPACE Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad
  • Patent number: 10026814
    Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm?3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 17, 2018
    Assignee: AZURSPACE Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
  • Publication number: 20180012985
    Abstract: A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.
    Type: Application
    Filed: September 8, 2017
    Publication date: January 11, 2018
    Applicant: AZURSPACE Solar Power GmbH
    Inventors: Stephan LUTGEN, Saad MURAD
  • Publication number: 20170373156
    Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
    Type: Application
    Filed: September 11, 2017
    Publication date: December 28, 2017
    Applicant: AZURSPACE Solar Power GmbH
    Inventors: Stephan LUTGEN, Saad MURAD, Ashay CHITNIS
  • Patent number: 9786744
    Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: October 10, 2017
    Assignee: AZURSPACE Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
  • Patent number: 9773896
    Abstract: A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: September 26, 2017
    Assignee: AZURSPACE Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad
  • Publication number: 20170077242
    Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
    Type: Application
    Filed: November 2, 2016
    Publication date: March 16, 2017
    Applicant: AZURSPACE Solar Power GmbH
    Inventors: Stephan LUTGEN, Saad MURAD, Ashay CHITNIS
  • Patent number: 9496349
    Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: November 15, 2016
    Assignee: AZURSPACE Solar Power GmbH
    Inventors: Stephan Lutgen, Saad Murad, Ashay Chitnis
  • Patent number: 9397262
    Abstract: An optoelectronic semiconductor chip (1) is herein described which comprises a non-planar growth layer (2), which contains at least one first nitride compound semiconductor material, and an active zone (5), which contains at least one second nitride compound semiconductor material and is arranged on the growth layer (2), and a top layer (7), which is arranged on the active zone (5), the growth layer (2) comprising structure elements (4) at a growth surface (3) facing the active zone (5).
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: July 19, 2016
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Stephan Lutgen, Christoph Eichler, Marc Schillgalies, Desiree Queren
  • Publication number: 20150357419
    Abstract: An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management layer sequence including an interlayer structure arranged between and adjacent to a first and a second group-ill-nitride layer, wherein the interlayer structure comprises a group-ill-nitride interlayer material having a larger band gap than the materials of the first and second group-ill-nitride layers, and wherein a p-type-dopant-concentration profile drops, starting from at least 1×1018 cm-3, by at least a factor of two in transition from the interlayer structure to the first and second group-ill-nitride layers.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Applicant: AZURSPACE SOLAR POWER GMBH
    Inventors: Stephan LUTGEN, Saad MURAD, Ashay CHITNIS