Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

Abstract: Integrated circuits are supported by a semiconductor substrate wafer. Each integrated circuit includes an electrically active area. A thermally conductive protective structure is formed around the active areas of the various integrated circuits along scribe paths. The protective structure is located between the electrically active areas of the integrated circuits and a laser ablation area of the scribe paths. Separation of the integrated circuits is performed by scribing the semiconductor substrate wafer along the scribe paths. The process for scribing includes performing a laser ablation in the laser ablation area and then performing one of an etching or a physical scribing.

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.

Abstract: A semiconductor region includes an isolating region which delimits a working area of the semiconductor region. A trench is located in the working area and further extends into the isolating region. The trench is filled by an electrically conductive central portion that is insulated from the working area by an isolating enclosure. A cover region is positioned to cover at least a first part of the filled trench, wherein the first part is located in the working area. A dielectric layer is in contact with the filled trench. A metal silicide layer is located at least on the electrically conductive central portion of a second part of the filled trench, wherein the second part is not covered by the cover region.

Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

Abstract: A capacitive element includes a trench extending vertically into a well from a first side. The trench is filled with a conductive central section clad with an insulating cladding. The capacitive element further includes a first conductive layer covering a first insulating layer that is located on the first side and a second conductive layer covering a second insulating layer that is located on the first conductive layer. The conductive central section and the first conductive layer are electrically connected to form a first electrode of the capacitive element. The second conductive layer and the well are electrically connected to form a second electrode of the capacitive element. The insulating cladding, the first insulating layer and the second insulating layer form a dielectric region of the capacitive element.

Abstract: A split-gate memory cell includes a state transistor possessing a control gate and a floating gate and a selection transistor possessing a selection gate. The split-gate memory cell is programmed by applying, during a programming duration, a first voltage to the control gate, a second voltage to a drain of the state transistor and a third voltage to the selection gate of the selection transistor. The third voltage is transitioned during the programming duration between a first value and a second value greater than the first value.