Abstract: A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Abstract: A method can include, in a default mode of a memory device, decoding command data received on a unidirectional command address (CA) bus of a memory interface according to a first standard. In response to decoding a mode enter command, placing the memory device into an alternate management mode. In the alternate management mode, receiving alternate command data on the CA bus, and in response to receiving a command execute indication on the CA bus, decoding alternate command data according to a second standard to execute an alternate command. In response to decoding a mode exit command received on the CA bus according to the first standard, returning the memory device to the default mode. The memory interface comprises the CA bus and a data bus, and the CA bus and data bus comprise a plurality of parallel input connections. Corresponding devices and systems are also disclosed.

Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.

Abstract: A method can include, in an integrated circuit device: at a unidirectional command-address (CA) bus having no more than four parallel inputs, receiving a sequence of no less than three command value portions; latching each command value portion in synchronism with rising edges of a timing clock; determining an input command from the sequence of no less than three command value portions; executing the input command in the integrated circuit device; and on a bi-directional data bus having no more than six data input/outputs (IOs), outputting and inputting sequences of data values in synchronism with rising and falling edges of the timing clock. Corresponding devices and systems are also disclosed.

Abstract: A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.

Abstract: A method includes using a memory address map, locating a first portion of an application in a first memory and loading a second portion of the application from a second memory. The method includes executing in place from the first memory the first portion of the application, during a first period, and by completion of the loading of the second portion of the application from the second memory. The method further includes executing the second portion of the application during a second period, wherein the first period precedes the second period.

Abstract: A memory device that includes a first port and a second port. The first port includes a first clock input, at least one first command address input, and at least one data input or output configured to transfer data in relation to the memory device. The second port includes a second clock input and at least one command, address, and data input/output (I/O) configured to receive command and address information from, and to transfer data in relation to the memory device. The memory device also includes a plurality of memory banks, in which two different memory banks may be accessed respectively by the first and the second ports concurrently. Other embodiments of the memory device and related methods and systems are also disclosed.

Abstract: A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.

Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.

Abstract: Disclosed are apparatus and methods for programming a plurality of nonvolatile memory (NVM) devices. Each NVM device self-generates and stores a unique encryption key. Each NVM device concurrently receives an image from a multiple-device programming system to which all the NVM devices are communicatively coupled. Each NVM device encrypts the received image using such NVM device's unique encryption key to produce a unique encrypted image for each NVM device. Each NVM device stores its unique encrypted image within a nonvolatile memory of such NVM device. The unique encryption key can then be securely transferred to a host device for decrypting the image accessed from one of the NVM devices.

Abstract: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input/outputs (I/Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

Abstract: An apparatus includes a non-volatile memory (NVM) device coupled to a host, the NVM device including a processing device to: receive a communication packet from a server via the host computing system that is coupled to the NVM device and communicatively coupled to the server, the communication packet comprising clear text data that requests to initiate secure communications; perform a secure handshake with the server, via communication through the host computing system, using a secure protocol that generates a session key; receive data, via the host computing system, from the server within a secure protocol packet, wherein the data is inaccessible to the host computing system; authenticate the data using secure protocol metadata of the secure protocol packet; optionally decrypt, using the session key, the data to generate plaintext data; and store the plaintext data in NVM storage elements of the NVM device.

Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.

Abstract: An apparatus including non-volatile memory to store a forensic key and data, the data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow writing the data, by the host computing system, to a region of the non-volatile memory; in response to a lock signal received from the host computing system, assert a lock on the region of the non-volatile memory, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access, by the external device, to the region of the non-volatile memory in response to verification of the forensic key received from the external device.

Abstract: A method is disclosed to estimate energy consumed by a component in a microcontroller during operation including identifying “event” activities, where the energy consumed by the component may be determined by the number of events executed by the component, and “duration” activities, where the energy consumed may be determined by the duration of time required to execute of the activity, and determining the energy consumed by the component based on the number of events/duration of time and an energy coefficient which corresponds to the amount of energy consumed by the component to execute the activity, under given operating conditions. In an embodiment, data transfers at a bus interface may represent event activities. Apparatus to estimate the energy consumed is disclosed including bus monitors to receive signals representing data transfers at a bus interface and provide signals indicating the number of data transfers executed.

Abstract: A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.

Abstract: A method can include, by operation of a host device, initiating a first transaction with at least a first device on a serial bus in synchronism with a clock, the first transaction having a predetermined response latency. The host device can initiate a second transaction on the serial bus in synchronism with the clock signal during the response latency. The first transaction and second transaction can be completed on the serial bus in synchronism with the clock. The serial bus is configured to transmit instruction data identifying transactions, target data identifying a destination for transactions, and data for transactions. Corresponding devices and systems are also disclosed.

Abstract: A device can include a plurality of regions, each region including a plurality of nonvolatile memory cells; a permission store configured to store a set of permission values, including at least one permission value for each region in a nonvolatile fashion; and access control circuits configured to control access to each region according to the permission value for the region, including one or more of requiring authentication to access the region, encrypting data read from the region, and decrypting data for storage in the region. Related methods and systems are also disclosed.

Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.