Abstract: A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to.

Abstract: A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to.

Abstract: Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the client component circuitry over the bus on a periodic time basis. The periodic time basis is dictated by a host component time period and the client component time period is greater than the host component time period. The client component circuitry is configured to initiate a reset procedure if the client component time period expires which indicates that the initial client value was not received at a next time on the periodic time basis dictated by the host component time period.

Abstract: Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the client component circuitry over the bus on a periodic time basis. The periodic time basis is dictated by a host component time period and the client component time period is greater than the host component time period. The client component circuitry is configured to initiate a reset procedure if the client component time period expires which indicates that the initial client value was not received at a next time on the periodic time basis dictated by the host component time period.

Abstract: One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another. Techniques employed facilitate efficient digital data transfer between the first and second domains while conserving valuable semiconductor real estate.

Abstract: A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40).

Abstract: According to one exemplary embodiment, a RAM employing system includes a RAM and a RAM controller coupled to the RAM. The RAM employing system further includes a command queue, which is configured to receive time encoded RAM commands from the RAM controller. The RAM is configured to retrieve, decode, and execute each of the time encoded RAM commands in the command queue.

Abstract: In the operation of a mobile device (such as a cellular telephone or a PDA, i.e. Personal Digital Assistant), which mobile device includes a mobile terminal and a memory module, certain operational signals of the mobile device are multiplexed and demultiplexed, resulting in efficient device bus utilization and reduced device pin count.

Abstract: One embodiment of the present invention relates to a method for communicating NOR-type flash specific memory commands from a DRAM memory controller to a NOR-type flash memory array without disrupting DRAM operation. In this embodiment flash specific commands are channeled from the DRAM controller to the flash device by using the DRAM protocol as a transport layer. Data to be written to the NOR-type flash memory array are loaded into a data register and a sequence of programming commands are loaded into a mode register as a series of mode register write operations. Once the entire sequence of programming commands is loaded the NOR-type flash memory array the data in the data register is loaded into the NOR-type flash memory array. Other methods and circuits are also disclosed.

Abstract: A memory buffering system is disclosed that arbitrates bus ownership through all arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures.

Abstract: A system is presented that facilitates masking data in write data bound for a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends a write command and write data to the memory array and the memory array updates data contained therein based upon the write command and write data. If the write operation requires a byte mask, the controller sends a byte mask command via a command bus linking the controller and the memory array. Accordingly, separate and dedicated byte mask pins or bus is not necessary to convey byte mask information.

Abstract: A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.

Abstract: A multi media card includes a plurality of memory modules and an extraneous command decoder. The extraneous command decoder decodes a predetermined command for determining a selected memory module to be accessed from the plurality of memory modules, when a predetermined bit of the predetermined command is set to a predetermined logic level.

Abstract: A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40). Bus latencies are masked by at least overlapping transmitting the first portion of the transmit frame while downloading the second portion.

Abstract: A multi media card includes a plurality of memory modules and an extraneous command decoder. The extraneous command decoder decodes a predetermined command for determining a selected memory module to be accessed from the plurality of memory modules, when a predetermined bit of the predetermined command is set to a predetermined logic level.

Abstract: The invention relates to a method and an apparatus for receiving and transmitting asynchronous transfer mode (ATM) cell streams over a bus. The invention provides a method for receiving ATM cells in a host from a client over a bus, comprising the steps of determining whether an ATM cell in a first storage device within the client is ready to be transferred over the bus to a second storage device within the host, preventing overflow of the second storage device by calculating a first available cell space in the second storage device as a function of a write value, a read value image and a size value of the second storage device, and transferring an ATM cell from the first storage device to the second storage device.

Abstract: One or more aspects of the present invention pertain to transferring digital data between first and second domains, where a first clock of the first domain operates at a first frequency and a second clock of the second domain operates at a second frequency, where the first frequency is higher than the second frequency, and where the first and second clocks have arbitrary phase relationships relative to one another. Techniques employed facilitate efficient digital data transfer between the first and second domains while conserving valuable semiconductor real estate.

Abstract: A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40).

Abstract: A wireless computer system (30) is formed to have a host section (31) and a wireless hardware section (40). A first portion of a transmission frame is formed in system memory (36) of a host section (31) and a second portion of the transmission frame is formed in the wireless hardware section (40). The wireless hardware section (40) begins transmitting the first transmission frame portion while downloading the second transmission frame portion from the system memory (36) into the wireless hardware section (40).

Abstract: The invention relates to an apparatus and a method for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers. The invention provides a method for executing a read request over a PCI bus by transferring the requested data from a main memory of a PCI card to a device located on the PCI bus, comprising the steps of obtaining an access request from a read access queue, transferring, by a first DMA transfer, the requested data from the main memory to a buffer memory on the PCI card, and transferring, by a second DMA transfer, the data from the buffer memory to the device.