Abstract: A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.

Abstract: A method of preparing a coating solution, comprising the steps of providing a first solution comprising a lower alcohol; a polyethylene glycol; a complexing agent; and water; providing a second solution comprising a higher alcohol; and at least one metal alkoxide, wherein the metal in said at least one metal alkoxide is selected from the group consisting of zirconium, aluminium, titanium, tantalum and yttrium; forming a sol-gel solution by mixing said first and second solutions and thereby hydrolyzing said at least one metal alkoxide to a metal oxide and an alcohol; forming a concentrated solution by removing said lower alcohol and the alcohol resulting from the hydrolysis of said at least one metal alkoxide; and forming a coating solution by adding a medium alcohol to said concentrated solution.

Abstract: A device and method for depositing a protective layer on a material during a plasma etching procedure in the course of fabricating semiconductor components, in particular in the course of fabricating DRAM chips, characterized in that the plasma has at least one precursor which, during the plasma etching procedure, together with a constituent of the plasma at least partially forms a protective layer on a planar region of the material and, characterized by a means for feeding the at least one precursor into the plasma, in which case, by means of the at least one precursor, during the plasma etching procedure, together with a constituent of the plasma, a protective layer can at least partially be deposited on a planar region of the material.

Abstract: The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

Abstract: In a method for the treatment of material, in particular in the fabrication of semiconductor components, at least one partial region of the material is implanted with ions in a targeted manner. Afterward or in a later method step, a step of etching the material is performed, the etching rate of this method step being altered in a targeted manner by the implanted ions.

Abstract: An apparatus includes a plasma process chamber and a support element capable of supporting a substrate inside the plasma process chamber. At least one plasma control element is placed adjacent to a peripheral portion of the support element such that the plasma control element is capable of influencing a plasma inside the plasma process chamber if an electric field is applied thereto. At least one voltage generator is connected to the plasma control element. The plasma control element is movable inside the process chamber such that it can be set to any of at least two different positions.

Abstract: A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Abstract: The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10?) made of silicon oxide and an overlying second hard mask layer (15; 15?) made of silicon; providing a masking layer (30; 30?) made of silicon oxide above and laterally with respect to the second hard mask layer (15; 15?) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (1); providing a photoresist mask (25) above the masking layer (30; 30?) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (1); opening the masking layer (30; 30?) in a first plasma process using the photoresist mask (25), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer (10; 10?) and second hard mask layer (15; 15?) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate (1) in a fou

Abstract: Process for producing an etching mask on a microstructure, in particular a semiconductor structure with trench capacitors, and corresponding uses of the etching mask which allow for extremely thin photoresist layers to be employed.

Abstract: The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.

Abstract: In order to monitor the etching operation for a regular depth structure in a semiconductor substrate, a radiation source is used to irradiate, in large-area fashion, the semiconductor substrate in the region of the depth structure during the etching operation at a predetermined angle of incidence with respect to the surface of the semiconductor substrate with an electromagnetic radiation whose wavelength lies in the infrared region, a radiation detector is used to continuously detect the intensity of the reflected radiation at an angle of reflection—corresponding to the angle of incidence—with respect to the surface of the semiconductor substrate, and an evaluation unit is used to determine the depth of the etched structure and/or the quality of the etched structure with regard to the regularity thereof from the recorded intensity profile.

Abstract: The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10?) made of silicon oxide and an overlying second hard mask layer (15; 15?) made of silicon; providing a masking layer (30; 30?) made of silicon oxide above and laterally with respect to the second hard mask layer (15; 15?) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (1); providing a photoresist mask (25) above the masking layer (30; 30?) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (1); opening the masking layer (30; 30?) in a first plasma process using the photoresist mask (25), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer (10; 10?) and second hard mask layer (15; 15?) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate (1) in a fou

Abstract: A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Abstract: A method for fabricating a semiconductor component includes: deposition of a polysilicon layer on a substrate, deposition of a precursor layer on the polysilicon layer, and deposition of a protective layer on the precursor layer. A crystalline transformation occurs in the precursor layer at a first temperature to form an electrode layer. The layers are patterned to form an electrode stack, and the polysilicon layer is oxidized at a second temperature such that no crystalline transformation occurs in the electrode layer.

Abstract: To form a pattern in a semiconductor substrate, a buffer layer, which is formed as a carbon layer, is produced between a photoresist layer and an antireflective layer, which is formed on the substrate. The pattern is produced in the photoresist layer by means of a lithography step, and then it is transferred to the layers arranged below in a subsequent step.

Abstract: A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.

Abstract: A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.

Abstract: The optimization of a CMP process provides the use of an auxiliary layer (4) between a dielectric (1) in the vicinity of patterned portions and a layer of a liner (2). If the liner (2) is perforated in the CMP process, then the undercutting of the liner (2) by the chemical removal of the auxiliary layer (4) simplifies the process overall. Advantages are significantly lower defect densities due to CMP scratches, fewer short circuits, fewer alignment errors.

Abstract: The present invention provides a process for producing an etching mask on a microstructure, in particular a semiconductor structure with one or more trench capacitors (5), which includes the following steps: providing a lower first, a middle second and an upper third hard-mask layer (60; 70; 80) on a surface of the microstructure, the third hard-mask layer (80) being significantly thinner than the first and second hard-mask layers (60; 70); providing a photoresist mask (100) above the third hard-mask layer (80); patterning the third hard-mask layer (80) by etching chemistry using the photoresist mask (100); patterning the second hard-mask layer (70) by etching chemistry using the patterned third hard-mask layer (80), with the photoresist mask (100) being removed at the same time; patterning the first hard-mask layer (60) by etching chemistry using the patterned second hard-mask layer (70), with the third hard-mask layer (80) being removed at the same time; and removing the patterned second hard-mask layer (70

Abstract: A method for fabricating a semiconductor structure includes providing a semiconductor substrate and a sacrificial layer between a layer to be patterned and a resist layer, patterning the resist layer to form a patterned resist layer; selectively etching the sacrificial layer with a taper angle so as to reduce the dimensions within the sacrificial layer in the etching direction which are prescribed by depressions situated in the patterned resist layer, and selectively etching the layer to be patterned using the sacrificial layer etched with a taper angle as a mask. The present invention also relates to a method for fabricating a semiconductor structure in which two sacrificial layers are used.