Abstract: The invention relates to a production method for a semiconductor component, with a substrate (1) and an electrode stack (7, 9′, 11′, 13), comprising a polysilicon electrode layer (7) and a tungsten-containing electrode layer (9′) arranged thereon.

Abstract: A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.

Abstract: Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.

Abstract: Metal/metal contacts are formed as part of a multilayer metallization in an integrated circuit on a semiconductor wafer. The application of an insulation layer on a metal level is followed by a lithography step using a photoresist mask to define contact holes on the insulation layer, followed by anisotropic etching of the insulation layer in order to produce the contact holes. Then, a chemical dry etch that removes the photoresist mask and a chemical-physical dry etch that removes organic impurities which accumulate during the chemical dry etch are successively carried out in a vacuum. Subsequently, a metal deposition step is carried out in order to fill the contact holes.

Abstract: A method for fabricating a trench isolation for electrically active components in a semiconductor component. A mask is applied to a semiconductor substrate. Subsequently, a trench having side walls is formed in the semiconductor substrate by performing a dry etching process using at least one etching gas such that during the dry etching process, polymers are produced that at least partly cover the side walls of the trench and thereby at least partially protect the side walls against an etching attack from the etching gas. The etching gas is provided with a compound that is selected from the group consisting of at least one hydrocarbon compound and a fluorinated hydrocarbon compound. The trench is filled with an insulating oxide.

Abstract: A simple to manufacture conductor structure is described which requires only a small number of process steps. The conductor structure contains a structured, first insulating layer to which a first passivation layer is applied. A layer of conductive material is applied thereto and in turn a second passivation layer is applied to the layer of conductive material. A hard mask is applied to the second passivation layer. The layer of conductive material is removed in regions defined by the hard mask. The first passivation layer is removed in the regions defined by the hard mask by sputtering and is at least partially deposited again on the side wall of the layer of conductive material.

Abstract: The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound and at least one oxidizing agent. The concentration of the oxidizing agent is thereby set higher than the concentration of the halogen compound.

Abstract: Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.

Abstract: Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing, gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.

Abstract: A method of producing a semiconductor device is described. The semiconductor device has a semiconductor chip with wiring terminals, conductor tracks for the electrical connection of the semiconductor chip, and a component of a housing configuration that contains organic, silicon-containing material. For this purpose, the semiconductor chip is applied to the component of the housing configuration and permanently connected to it. The conductor tracks and/or the wiring terminals are subsequently subjected to a cleaning process, in which silicon-containing material adhering to a surface is eliminated. The conductor tracks are subsequently connected in an electrically conducting manner to the wiring terminals. The contact quality of these electrical connections is noticeably improved by the cleaning process provided.

Abstract: A method for fabricating a trench isolation for electrically active components in a semiconductor component. A mask is applied to a semiconductor substrate. Subsequently, a trench having side walls is formed in the semiconductor substrate by performing a dry etching process using at least one etching gas such that during the dry etching process, polymers are produced that at least partly cover the side walls of the trench and thereby at least partially protect the side walls against an etching attack from the etching gas. The etching gas is provided with a compound that is selected from the group consisting of at least one hydrocarbon compound and a fluorinated hydrocarbon compound. The trench is filled with an insulating oxide.

Abstract: A method for the shrink-hole-free filling of trenches in semiconductor circuits which utilizes selective growth of a layer to be applied is described. In the method, a layer of a selective growing material is applied simultaneously to a growth-promoting layer and to a growth-inhibiting layer. Wherein raised portions which, before the layer of selective growing material is applied, are covered by the growth-inhibiting layer at least on their sides. After the growth-inhibiting layer has been applied, the growth-promoting layer is generated by anisotropic treatment on surfaces parallel to the substrate on and between the raised portions and the layer is then removed again on surfaces parallel to the substrate on the raised portions. The method makes it possible to produce in a particularly simple manner a pattern on the raised portions of which are covered by the growth-inhibiting layer on their sides and on their top whereas the bottom of trenches is covered with a growth-promoting layer.

Abstract: The present invention relates to a dielectric filling for electrical wiring planes of an integrated circuit. The electrical wiring of the integrated circuit comprises a base body on which track and passivation planes can already be disposed; a conductive layer which is disposed on the base body and is patterned in such a manner that it exhibits a first conductor track, a second conductor track and a trench between the first conductor track and the second conductor track; at least one dielectric layer is disposed on the conductive layer and at least partially fills the trench, the preferred material of the dielectric layer being the polymer material polybenzoxazole.

Abstract: The optimization of a CMP process provides the use of an auxiliary layer (4) between a dielectric (1) in the vicinity of patterned portions and a layer of a liner (2). If the liner (2) is perforated in the CMP process, then the undercutting of the liner (2) by the chemical removal of the auxiliary layer (4) simplifies the process overall. Advantages are significantly lower defect densities due to CMP scratches, fewer short circuits, fewer alignment errors.

Abstract: Metal/metal contacts are formed as part of a multilayer metallization in an integrated circuit on a semiconductor wafer. The application of an insulation layer on a metal level is followed by a lithography step using a photoresist mask to define contact holes on the insulation layer, followed by anisotropic etching of the insulation layer in order to produce the contact holes. Then, a chemical dry etch that removes the photoresist mask and a chemical-physical dry etch that removes organic impurities which accumulate during the chemical dry etch are successively carried out in a vacuum. Subsequently, a metal deposition step is carried out in order to fill the contact holes.

Abstract: Doped polysilicon layers and layered polysilicon structures are produced, and the layers and layered structures are structured. The doping is distinguished by the fact that the doping compound is added as a process gas during the chemical vapor deposition of the polysilicon to define the doping profile. The feed of dopant to the process gas is stopped toward the end of the vapor deposition, with the result that a boundary layer of undoped silicon is deposited. As a result, a favorable surface quality and better adhesion to a neighboring layer is obtained. The structuring process comprises an at least three-step etching process in which a fluorine containing gas is used for etching in a first step, a chlorine-containing gas is used for etching in a second step and a bromine-containing gas is used for etching in a third step. The invention also encompasses wafers and semiconductor chips produced with the novel doping and/or structuring method.

Abstract: The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound and at least one oxidizing agent. The concentration of the oxidizing agent is thereby set higher than the concentration of the halogen compound.

Abstract: In a process for the anisotropic dry etching of an organic antireflection layer, the etching gases used are substantially hydrogen and nitrogen.

Abstract: A simple to manufacture conductor structure is described which requires only a small number of process steps. The conductor structure contains a structured, first insulating layer to which a first passivation layer is applied. A layer of conductive material is applied thereto and in turn a second passivation layer is applied to the layer of conductive material. A hard mask is applied to the second passivation layer. The layer of conductive material is removed in regions defined by the hard mask. The first passivation layer is removed in the regions defined by the hard mask by sputtering and is at least partially deposited again on the side wall of the layer of conductive material.

Abstract: A method of producing a semiconductor device is described. The semiconductor device has a semiconductor chip with wiring terminals, conductor tracks for the electrical connection of the semiconductor chip, and a component of a housing configuration that contains organic, silicon-containing material. For this purpose, the semiconductor chip is applied to the component of the housing configuration and permanently connected to it. The conductor tracks and/or the wiring terminals are subsequently subjected to a cleaning process, in which silicon-containing material adhering to a surface is eliminated. The conductor tracks are subsequently connected in an electrically conducting manner to the wiring terminals. The contact quality of these electrical connections is noticeably improved by the cleaning process provided.