INTEGRATED CIRCUIT STRUCTURE WITH METAL CRACK STOP AND METHODS OF FORMING SAME
Embodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop and methods of forming the same. An IC structure according to embodiments of the present disclosure can include an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.
Aspects of the disclosure relate generally to structures and manufacturing processes of integrated circuits (ICs). More specifically, embodiments of the present disclosure include an IC structure with a metal crack stop therein, and process of forming the IC structure with the metal crack stop.
Each IC of a particular device can be made up of billions of interconnected devices, such as transistors, resistors, capacitors, and diodes, located on one or more chips of semiconductor substrate material. The quality and viability of a product including an IC therein can be at least partially dependent on the techniques used for fabricating the IC and the structure of various components therein. Fabrication of an IC can include two phases: front-end-of-line processes (FEOL) and back-end-of-line processes (BEOL). FEOL generally includes fabrication processes performed on a wafer up to and including the formation of a first “metal layer,” i.e., a metal wire for connecting several semiconductor devices together. BEOL generally includes fabrication processes following the formation of the first metal layer, including the formation of all subsequent metal layers. To provide greater scaling and sophistication of the fabricated device, the number of metal layers can be varied to suit a particular application, e.g., by providing four to six metal layers, or as many as, in a further example, sixteen or more metal layers.
As the total number of devices in each IC product continues to increase, the resilience of an IC structure to side-effects of processing and/or general wear has become increasingly significant. For example, the separation of metal layers from one another (i.e., delamination) during a dicing process can become significant where cracks form at the edge of a product and propagate toward the devices included therein. Even where dummy materials (sometimes known as “crack stops”) are formed near the perimeter of a manufactured device to prevent or slow the growth of a crack, a formed crack may nevertheless circumvent the crack stop in some instances.
BRIEF SUMMARYA first aspect of the disclosure provides an integrated circuit (IC) structure including: an insulator positioned over a substrate; a barrier film positioned over the insulator; an interlayer dielectric positioned over the barrier film; and a metal crack stop positioned over the substrate and laterally adjacent to each of the insulator, the barrier film, and the interlayer dielectric, wherein the metal crack stop includes a sidewall having a first recess therein, and wherein a horizontal interface between the barrier film and the interlayer dielectric intersects the sidewall of the metal crack stop.
A second aspect of the disclosure provides a method of forming an integrated circuit (IC) structure. Methods of forming an integrated circuit structure according to embodiments of the present disclosure can include: providing a structure including: a sacrificial metal positioned over a substrate and laterally adjacent to an insulator, a first barrier film positioned over and contacting each of the sacrificial metal region and the insulator, and a first interlayer dielectric positioned over and contacting the first barrier film; forming an opening over the substrate by removing a portion of first interlayer dielectric, a portion of the first barrier film, and the sacrificial metal; and forming a first metal crack stop within the opening and over the substrate.
A third aspect of the disclosure provides a method of forming an integrated circuit (IC) structure. Methods of forming an integrated circuit structure according to embodiments of the present disclosure can include: providing a structure including: a sacrificial metal positioned over a substrate and laterally adjacent to an insulator, a first barrier film positioned over and contacting each of the sacrificial metal and the insulator, and a first interlayer dielectric positioned over and contacting the first barrier film; forming an opening over the substrate by removing a first portion of the first interlayer dielectric, a first portion of the first barrier film, and the sacrificial metal, wherein a second portion of the interlayer dielectric and a second portion of the first barrier film remain positioned over the sacrificial metal; and forming a first metal crack stop within the opening, wherein the first metal crack stop includes a first recess intersecting an interface between the first barrier film and the first interlayer dielectric.
The illustrative aspects of the present disclosure are designed to solve the problems herein described and/or other problems not discussed.
These and other features of this disclosure will be more readily understood from the following detailed description of the various aspects of the disclosure taken in conjunction with the accompanying drawings that depict various embodiments of the disclosure, in which:
It is noted that the drawings of the disclosure are not to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements among the drawings.
DETAILED DESCRIPTIONEmbodiments of the present disclosure provide an integrated circuit (IC) structure with a metal crack stop, including structures for impeding or altogether preventing delamination cracks from propagating away from a perimeter of the IC to active devices therein. The present disclosure also contemplates methods for fabricating IC structures described herein. Generally, an IC structure according to the present disclosure can include an insulator positioned over a substrate, a barrier film positioned over the insulator, and an interlayer dielectric positioned over the first barrier film. The IC structure can also include a metal crack stop positioned over the substrate, e.g., over a semiconductor region of the substrate separated from other regions by shallow trench isolations (STIs). The metal crack stop can be laterally and directly adjacent to each of the insulator, the barrier film, and the insulator dielectric. Furthermore, the metal crack stop can include a sidewall with a first recess therein. The first recess can be positioned, e.g., adjacent to a horizontal interface between the first barrier film and the interlayer dielectric, and can intersect a sidewall of the metal crack stop. Among other things, recesses included in the metal crack stop can accommodate and/or trap horizontally-propagating delamination cracks therein, such that the cracks cannot continue propagating without doing so in a partially vertically and/or horizontally reverse direction to bypass the metal crack stop.
Referring to
Semiconductor regions 12 can be composed of any currently known or later developed semiconductor material, which may include without limitation: silicon, germanium, silicon carbide, and substances consisting essentially of one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3ASY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions, each greater than or equal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relative mole quantity). Other suitable substances can include II-VI compound semiconductors having a composition ZnA1CdA2SeB1TeB2, where A1, A2, B1, and B2 are relative proportions each greater than or equal to zero and A1+A2+B1+B2=1 (1 being a total mole quantity). Furthermore, the entirety of each semiconductor region 12 or a portion thereof may be strained. Substrate 10 can also include shallow trench isolations (STIs) 14 positioned laterally between, e.g., semiconductor regions 12. STI(s) 14 can be formed by removing portions of substrate 10 to form trenches and then filling the trenches with an electrically insulative material, e.g., one or more of the insulating materials described elsewhere herein.
An insulator 16 can be formed on and positioned above substrate 10. Insulator 16 may be composed of any insulating material such as SiO2, SiN, porous SiOx, and/or doped SiOx, and other currently known or later developed materials having similar properties.
A sacrificial metal 18 and a conductive region 20 can be formed on substrate 10, and within insulator 16. Sacrificial metal 18 and conductive region 20 can be composed of any currently known or later-developed conductive material, such as a metal, and in an example embodiment can be formed of the same material. Although sacrificial metal 18 and conductive region 20 are distinct structural components, sacrificial metal 18 and conductive region 20 can have the same material composition and more specifically can be yielded from the same process steps. In an example embodiment, sacrificial metal 18 and conductive region 20 can be formed by selectively removing portions of insulator 16 to form two trenches, and forming tungsten therein, e.g., by a metal deposition process. Although not shown explicitly in
Structure 2 can include a barrier film 22 formed over insulator 16, sacrificial metal 18, and conductive region 20. An interlayer dielectric (ILD) 24, in turn, can be formed over barrier film 22. Barrier film 22 can be embodied as any currently known or later developed “low-k” insulating or dielectric material, such as one or more of those discussed herein with respect to insulator 16. Barrier film 22 can be adapted to insulate adjacent metal-level layers of in an integrated circuit, and can have a dielectric constant of at most approximately 3.9, e.g., the dielectric constant of silicon dioxide (SiO2). Where barrier film 22 includes a low-k material, the properties of barrier film 22 can reduce or prevent interlayer conductivity, i.e., “cross talk” between adjacent layers. ILD 24, also known as an “inter-metal dielectric” or “inter-level dielectric,” can include any dielectric material capable of electrically separating closely spaced interconnect lines positioned in multilevel metallization regions of an IC. ILD 24 can be composed of a material with a lower dielectric constant than barrier film 22, and in an embodiment can be composed of a material having a dielectric constant between approximately 1.0 and approximately 2.0, or in any event less than approximately 3.9. As discussed elsewhere herein (e.g., relative to
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“Etching” generally refers to the removal of material from a substrate (or structures formed on the substrate), and is often performed with a mask (e.g., mask 26) in place so that material may selectively be removed from a structure, while leaving the remaining material unaffected. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as a metal), while leaving another material (such as insulator materials) relatively intact. The ability to selectively etch particular materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., a metal) isotropically, but a wet etch may also etch monocrystalline materials (e.g., silicon and/or insulators) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive-ion etching (RIE) operates under conditions intermediate between sputter and plasma etching and may be used to produce deep, narrow features, such as shallow trench isolation (STI) trenches.
In the case of RIE, a phenomenon known as “RIE lag” can permit exposure of sacrificial metal 18 while leaving a portion of barrier film 22 intact over conductive region 20. Specifically, a material subject to the same instance of RIE may be etched at different rates in different locations, particularly where a mask on the material exposes a different cross-sectional area of the material at two different locations. In general, RIE lag will cause smaller cross-sections of a material to be etched more slowly than larger cross-sections of the same material. As is shown in
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Referring now to
The forming of first metal crack stop 30 can also include forming liner 32 over the exposed portion of conductive region 20, and forming vias 34 over liner 32 and conductive region 20. Vias 34 can be composed of any currently known or later developed conductive material, and more specifically can be composed of the same materials used to form first metal crack stop 30. Each via 34 can also include multiple sub-sections therein. For example, a portion of via 34 positioned proximal to conductive region 20 can be known as a “trench via,” while other portions of via 34 can be known simply as a “via.” Vias 34 can be formed, e.g., simultaneously with first metal crack stop 30 using a shared deposition and polishing process. Although first metal crack stop 30 and vias 34 can be formed with the same process step, first metal crack stop 30 can reduce the propagation of delamination cracks as discussed herein, while vias 34 can transmit electric current between layers of an IC structure as is also discussed herein.
Turning to
During stress events such as the dicing of chips from a larger structure, delamination cracks traveling horizontally along an interface between barrier film 22 and ILD 24, or between barrier film 22 and insulator film 16, will be stopped at an interface with a single, one-piece a vertical sidewall S of first metal crack stop 30. That is, delamination cracks propagating along these interfaces would hit a metal wall and will meet no horizontal interface through which the crack can propagate to the other side of first metal crack stop 30. Cracks would therefore need to move vertically upwards or downwards along sidewall S of first metal crack stop 30 in order to reach another horizontal interface for further propagation. As discussed elsewhere herein, sidewall S of metal crack stop 30 can also include recesses therein for trapping and/or further impeding horizontally propagated delamination cracks.
Turning to
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Structure 50 can, optionally, include at least one nitride region 60 (e.g., a middle of line (MOL) nitride) extending laterally through insulator 16. Nitride region 60 can have electrically insulating properties, similar to a remainder of insulator 16, yet can include a different chemical composition. More specifically, nitride region 60 can be composed of a material with a greater resistance to wet etching than a remainder of insulator 16, as discussed elsewhere herein. Where insulator 16 includes a nitride material, nitride region 60 can be composed of a different nitride material with a greater ability to resist wet etching than a remainder of insulator 16.
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The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
Claims
1-8. (canceled)
9. A method of forming an IC structure, the method comprising:
- providing a structure including: a sacrificial metal positioned over a substrate and laterally adjacent to an insulator, a first barrier film positioned over and contacting each of the sacrificial metal and the insulator, and a first interlayer dielectric positioned over and contacting the first barrier film;
- forming a first opening over the substrate by removing a portion of first interlayer dielectric, a portion of the first barrier film, and the sacrificial metal; and
- forming a first metal crack stop within the first opening and over the substrate, wherein the first metal crack stop includes a continuous metal fill contacting the substrate and laterally adjacent to each of the insulator, the first barrier film, and the first interlayer dielectric.
10. The method of claim 9, further comprising:
- forming a second barrier film over the first interlayer dielectric and an upper surface of the first metal crack stop;
- forming a second interlayer dielectric over the second barrier film;
- forming a second opening within the second barrier film and the second interlayer dielectric by removing a portion of the second interlayer dielectric and the second barrier film to expose an upper surface of the first metal crack stop; and
- forming a second metal crack stop within the second opening and over an upper surface of the second interlayer dielectric, wherein the second metal crack stop includes the continuous metal fill of the first metal crack stop.
11. The method of claim 9, further comprising forming a liner within the first opening and in contact with at least the substrate, the insulator, the interlayer dielectric, and the first barrier film before the forming of the first metal crack stop.
12. The method of claim 11, wherein the liner includes one of tantalum nitride (TaN) and tantalum (Ta).
13. The method of claim 9, wherein the structure further includes a conductive region laterally displaced from the sacrificial metal, the sacrificial metal having a greater width than the conductive region, wherein the removing of the portion of the first interlayer dielectric and the first barrier film positioned over the sacrificial metal includes removing a portion of the first interlayer dielectric positioned over the conductive region to expose a portion of the first barrier film positioned over the conductive region.
14. The method of claim 13, further comprising selectively removing the portion of the first barrier film positioned over the conductive region before forming the first metal crack stop.
15. The method of claim 14, further comprising forming a via over the conductive region during the forming of the first metal crack stop, wherein an upper surface of the via is substantially coplanar with an upper surface of the first interlayer dielectric and an upper surface of the first metal crack stop.
16. A method of forming an IC structure, the method comprising:
- providing a structure including: a sacrificial metal positioned over a substrate and laterally adjacent to an insulator, a first barrier film positioned over and contacting each of the sacrificial metal and the insulator, and a first interlayer dielectric positioned over and contacting the first barrier film;
- forming an opening over the substrate by removing a first portion of the first interlayer dielectric, a first portion of the first barrier film, and the sacrificial metal, wherein a second portion of the interlayer dielectric and a second portion of the first barrier film remain positioned over the sacrificial metal; and
- forming a first metal crack stop within the opening, wherein the first metal crack stop includes a first recess intersecting an interface between the first barrier film and the first interlayer dielectric, and further includes a continuous metal fill contacting the substrate and laterally adjacent to each of the insulator, the first barrier film, and the first interlayer dielectric.
17. The method of claim 16, wherein the structure further includes a conductive region laterally displaced from the sacrificial metal, the sacrificial metal having a greater width than the conductive region, wherein the removing of the first portion of the first interlayer dielectric and the first barrier film positioned over the sacrificial metal includes removing a portion of the first interlayer dielectric positioned over the conductive region to expose the first barrier film positioned over the conductive region.
18. The method of claim 17, further comprising selectively removing the first barrier film positioned over the conductive region before forming the first metal crack stop.
19. The method of claim 18, further comprising forming a via over the conductive region during the forming of the first metal crack stop, wherein an upper surface of the via is substantially coplanar with an upper surface of the first interlayer dielectric and an upper surface of the first metal crack stop.
20. The method of claim 16, wherein the removing of the sacrificial metal further includes removing a portion of the insulator to expose a nitride region embedded within the insulator, and wherein the nitride region extends into the first metal crack stop.
Type: Application
Filed: Aug 27, 2015
Publication Date: Mar 2, 2017
Inventors: Jim S. Liang (Poughkeepsie, NY), Atsushi Ogino (Fishkill, NY), Roger A. Quon (Rhinebeck, NY), Stephen E. Greco (Stamford, CT)
Application Number: 14/837,461