Patents by Inventor Stephen Fischer

Stephen Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MFENCE and LFENCE micro-architectural implementation method and system
    Patent number: 9383998
    Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Stephen A. Fischer, Subramaniam Maiyuran, Shekoufeh Qawami
  • MFENCE and LFENCE micro-architectural implementation method and system
    Patent number: 9342310
    Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 17, 2016
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Stephen A. Fischer, Subramaniam Maiyuran, Shekoufeh Oawami
  • Method And Apparatus For A Zero Voltage Processor Sleep State
    Publication number: 20160098075
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Application
    Filed: December 11, 2015
    Publication date: April 7, 2016
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • METHOD AND APPARATUS FOR A ZERO VOLTAGE PROCESSOR SLEEP STATE
    Publication number: 20160091958
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 31, 2016
    Inventors: Sanjeev Jahagirdar, Varghese George, John Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Detection Of Return Oriented Programming Attacks
    Publication number: 20160085966
    Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 24, 2016
    Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
  • Detection of return oriented programming attacks
    Patent number: 9251348
    Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: February 2, 2016
    Assignee: Intel Corporation
    Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
  • Protection Against Return Oriented Programming Attacks
    Publication number: 20160012229
    Abstract: In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.
    Type: Application
    Filed: September 22, 2015
    Publication date: January 14, 2016
    Inventor: Stephen A. Fischer
  • Method and apparatus for a zero voltage processor
    Patent number: 9235258
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: January 12, 2016
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Method and apparatus for a zero voltage processor
    Patent number: 9223389
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Detection of return oriented programming attacks
    Patent number: 9223979
    Abstract: In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine a ROP metric based on a plurality of control transfer events. The ROP detection logic may also determine whether the ROP metric exceeds a threshold. The ROP detection logic may also, in response to a determination that the ROP metric exceeds the threshold, provide a ROP attack notification.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Stephen A. Fischer, Kevin C. Gotze, Yuriy Bulygin, Kirk D. Brannock
  • Method and apparatus for a zero voltage processor
    Patent number: 9223390
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 29, 2015
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Protection against return oriented programming attacks
    Patent number: 9177147
    Abstract: In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventor: Stephen A. Fischer
  • Protection against return oriented programming attacks
    Patent number: 9177148
    Abstract: In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventor: Stephen A. Fischer
  • Method and apparatus for a zero voltage processor sleep state
    Patent number: 9141180
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Sanjeev Jahagirdar, Varghese George, John Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • MFENCE and LFENCE micro-architectural implementation method and system
    Patent number: 9098268
    Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Stephen A. Fischer, Subramaniam Maiyuran, Shekoufeh Qawami
  • Method And Apparatus For A Zero Voltage Processor Sleep State
    Publication number: 20150169043
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Application
    Filed: February 25, 2015
    Publication date: June 18, 2015
    Inventors: Sanjeev Jahagirdar, Varghese George, John Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • METHOD AND APPARATUS FOR A NON-DETERMINISTIC RANDOM BIT GENERATOR (NRBG)
    Publication number: 20150055778
    Abstract: A hardware-based digital random number generator is provided. In one embodiment, a processor includes a digital random number generator (DRNG) to condition entropy data provided by an entropy source, to generate a plurality of deterministic random bit (DRB) strings, and to generate a plurality of nondeterministic random bit (NRB) strings, and an execution unit coupled to the DRNG, in response to a first instruction to read a seed value, to retrieve one of the NRB strings from the DRNG and to store the NRB string in a destination register specified by the first instruction.
    Type: Application
    Filed: December 29, 2011
    Publication date: February 26, 2015
    Inventors: George W. Cox, David Johnston, Martin G. Dixon, Stephen A. Fischer, Jason W. Brandt
  • Method And Apparatus For A Zero Voltage Processor
    Publication number: 20150058667
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Application
    Filed: September 25, 2014
    Publication date: February 26, 2015
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • Method And Apparatus For A Zero Voltage Processor
    Publication number: 20150052377
    Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
    Type: Application
    Filed: September 25, 2014
    Publication date: February 19, 2015
    Inventors: Sanjeev Jahagirdar, Varghese George, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Naveh, Shai Rotem
  • MFENCE and LFENCE micro-architectural implementation method and system
    Patent number: 8959314
    Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Intel Corporation
    Inventors: Salvador Palanca, Stephen Fischer, Subramaniam Maiyuran, Shekoufeh Qawami