Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract: A method and apparatus for limiting the exposure of hardware failure information is described. In one embodiment, an error reporting system of a processor may log various status and error address data into registers that retain their contents through a warm reset event. But the error reporting system of the processor may then determine whether the processor is operating in a trusted or secure mode. If not, then the processor's architectural state variables may also be logged into registers. But if the processor is operating in a trusted or secure mode, then the logging of the architectural state variables may be inhibited, or flagged as invalid.

Abstract: A hardware-based digital random number generator is provided. The digital random number generator is a randomly behaving random number generator based on a set of nondeterministic behaviors. The nondeterministic behaviors include temporal asynchrony between subunits, entropy source “extra” bits, entropy measurement, autonomous deterministic random bit generator reseeding and consumption from a shared resource.

Abstract: A processor includes a feature control unit to enable or disable one or more processor features individually in response to a user selectable setting. The feature control unit is adapted to disable the processor feature(s) if the user setting has not been updated in accordance with an input regardless of the value of the user setting prior to the update and to enable or disable the processor feature(s) in accordance with the updated user setting after it has been updated. The feature control unit may also include a lock unit to prevent changes to the updated user setting and a software feature selection unit to enable or disable processor features in response to a software feature selection setting and, optionally, only enable or disable processor features whose corresponding updated user setting is user enabled. The feature control unit may also include mechanisms to detect illegal feature selection conditions.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract: Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop.

Abstract: A memory circuit card is described, where the electrical and physical interface between the circuit card and a motherboard bus is independent of the memory type installed on the circuit card. The power supply voltage provided by the mother board is independent of the memory type, and persistent and non-persistent memory types may be used on a plurality of circuit cards installed on the motherboard. The power status of at least portions of the interfaces of the circuit card may be controlled at a future time based on signals received at an input of circuit card.

Abstract: Obtaining packet forwarding data for routing packets. The steps may include (1) receiving packet identification information including a virtual router identifier (VRID) and route data; (2) determining if the VRID of the received packet identification information belongs to a pre-defined set of VRIDs. Additionally, if the VRID of the received packet identification information belongs to the pre-defined set of VRIDs, then the method preferably performs the steps of: (1) converting the VRID into a shortened VRID; and (2) obtaining packet forwarding data by performing a ternary content addressable memory (TCAM) lookup using a short key. But if the VRID of the received packet identification information does not belong to the pre-defined set of VRIDs, then the method performs the step of obtaining packet forwarding data by performing a ternary content addressable memory (TCAM) lookup using a long key.

Abstract: Methods and systems for assigning package pins of an electronic device to logical pins of a device design to be implemented on the electronic device are disclosed. An example method includes receiving a technology description file for the electronic device, where the technology description file includes a catalog of information for the electronic device. The method further includes receiving a design description file for the device design, where the design description file includes a catalog of information for the device design. A database is created from the technology description file and the design description file, where the database is for use in assigning the package pins of the electronic device to the logical pins of the device design. The method still further includes programmatically assigning the package pins of the electronic device to the logical pins of the device design using the database.

Abstract: A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.

Abstract: A method and system for internal data loop back in a packet switch is provided. In some instances, the switch may be required to process multiple layers of a header within the data packet, such as when data is transferred over the network encapsulated with a TCP header at the Transport Layer to form a TCP packet, then encapsulated with an IP header at the Network Layer to form an IP packet, then encapsulated with one or more MPLS headers to form a MPLS packet, and then encapsulated with an Ethernet header at the Link Layer to form an Ethernet packet. In such an instance, the data packet can be iteratively processed by the packet switch using an internal loop back technique. An internal loop back may be accomplished by using a header providing internal routing instructions resulting in the data packet being routed directly from an egress queue back to an ingress queue whereupon the lower levels of the header can be processed.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract: The present invention provides compounds of formula I: in which: one of T1 and T4 is N and the other is C; T2 and T3 are independently N or C(CH2)nR2; X, Y and Z are independently N or C(CH2)nR3; R1 is Ar1 or R1 is C1-6alkyl optionally substituted with one or two groups Ar1; Ar1 is an optionally substituted cyclohexyl, piperidinyl, piperazinyl, morpholinyl, adamantyl, phenyl, naphthyl, a six membered heteroaromatic ring containing one, two or three nitrogen atoms, a five-membered heteroaromatic ring containing one, two, three or four heteroatoms chosen from O, N and S, at most one O or S atom being present, or a nine- or ten-membered bicyclic heteroaromatic ring in which phenyl or a six-membered heteroaromatic ring as defined above is fused to a six- or five-membered heteroaromatic ring as defined above; Ar is an optionally substituted phenyl, a six-membered heteroaromatic ring containing one, two or three nitrogen atoms or a five-membered heteroaromatic ring containing one, two, three or four heteroatoms cho

Abstract: A dynamic directory and tetrahedralization method. The dynamic directory of degree of freedom data for elements in a non-conformal mixed-element mesh includes elements subdividable into tetrahedral, in which a respective degree of freedom value is stored for each element, wherein the degree of freedom value is current as element subdivision proceeds. The tetrahedralization method includes providing a non-conformal mixed element mesh comprising elements subdividable into tetrahedra, identifying respective degree of freedom values for the elements in the mesh, and performing element subdivision based on the degree of freedom values of elements in the mesh.

Abstract: A method and apparatus for limiting the exposure of hardware failure information is described. In one embodiment, an error reporting system of a processor may log various status and error address data into registers that retain their contents through a warm reset event. But the error reporting system of the processor may then determine whether the processor is operating in a trusted or secure mode. If not, then the processor's architectural state variables may also be logged into registers. But if the processor is operating in a trusted or secure mode, then the logging of the architectural state variables may be inhibited, or flagged as invalid.

Abstract: A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.

Abstract: A method and system of deadlock free bus protection of memory and I/O resources during secure execution. A bus cycle initiates entry of a bus agent into a secure execution mode. The chipset records an identifier of the secure mode processor. Thereafter, the chipset intercedes if another bus agent attempts a security sensitive bus cycle before the secure mode processor exits the secure mode.

Abstract: A processor includes a feature control unit to enable or disable one or more processor features individually in response to a user selectable setting. The feature control unit is adapted to disable the processor feature(s) if the user setting has not been updated in accordance with an input regardless of the value of the user setting prior to the update and to enable or disable the processor feature(s) in accordance with the updated user setting after it has been updated. The feature control unit may also include a lock unit to prevent changes to the updated user setting and a software feature selection unit to enable or disable processor features in response to a software feature selection setting and, optionally, only enable or disable processor features whose corresponding updated user setting is user enabled. The feature control unit may also include mechanisms to detect illegal feature selection conditions.

Abstract: The present invention discloses a method and apparatus for saving and restoring registers. A single instruction is decoded. The single instruction moves contents of a plurality of registers associated with a functional unit in a processor to a memory; the processor operates under a plurality of operational modes and operand sizes. The single instruction arranges the contents in the memory according to a predetermined format into a plurality of groups, each group is aligned at an address boundary which corresponds to a multiple of 2N bytes. The predetermined format is constant for the plurality of operational modes and operand sizes. The single instruction retains the contents of the plurality of registers after moving.