Patents by Inventor Stephen H. Black
Stephen H. Black has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10315918Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.Type: GrantFiled: August 3, 2016Date of Patent: June 11, 2019Assignee: RAYTHEON COMPANYInventors: Roland W. Gooch, Buu Q. Diep, Stephen H. Black, Thomas A. Kocian, Adam M. Kennedy
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Patent number: 10262913Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.Type: GrantFiled: April 2, 2018Date of Patent: April 16, 2019Assignee: RAYTHEON COMPANYInventors: Roland W. Gooch, Buu Q. Diep, Adam M. Kennedy, Stephen H. Black, Thomas A. Kocian
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Publication number: 20180226309Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.Type: ApplicationFiled: April 2, 2018Publication date: August 9, 2018Inventors: Roland W. Gooch, Buu Q. Diep, Adam M. Kennedy, Stephen H. Black, Thomas A. Kocian
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Patent number: 9966320Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.Type: GrantFiled: September 20, 2016Date of Patent: May 8, 2018Assignee: RAYTHEON COMPANYInventors: Roland W. Gooch, Buu Q. Diep, Adam M. Kennedy, Stephen H. Black, Thomas A. Kocian
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Patent number: 9865519Abstract: A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.Type: GrantFiled: January 10, 2017Date of Patent: January 9, 2018Assignee: RAYTHEON COMPANYInventors: Stephen H. Black, Adam M. Kennedy
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Patent number: 9708181Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.Type: GrantFiled: February 19, 2016Date of Patent: July 18, 2017Assignee: Raytheon CompanyInventors: Adam M. Kennedy, Buu Q. Diep, Stephen H. Black, Tse E. Wong, Thomas Allan Kocian, Gregory D. Tracy
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Publication number: 20170148695Abstract: A surface defined by a wafer level package (WLP) region and an external region, and A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.Type: ApplicationFiled: January 10, 2017Publication date: May 25, 2017Inventors: Stephen H. Black, Adam M. Kennedy
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Patent number: 9570321Abstract: A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level package (WLP) region and an external region, and a layer of getter material is disposed on at least a portion of the external region. According to one embodiment, the external region comprises a saw-to-reveal (STR) region of the wafer.Type: GrantFiled: October 20, 2015Date of Patent: February 14, 2017Assignee: RAYTHEON COMPANYInventors: Stephen H. Black, Adam M. Kennedy
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Publication number: 20170011977Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.Type: ApplicationFiled: September 20, 2016Publication date: January 12, 2017Inventors: Roland W. Gooch, Buu Q. Diep, Adam M. Kennedy, Stephen H. Black, Thomas A. Kocian
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Patent number: 9520332Abstract: An electronic device and methods of manufacture thereof. One or more methods may include providing a lid wafer having a cavity and a surface surrounding the cavity and a device wafer having a detector device and a reference device. In certain examples, a solder barrier layer of titanium material may be deposited onto the surface of the lid wafer. The solder barrier layer of titanium material may further be activated to function as a getter. In various examples, the lid wafer and the device wafer may be bonded together using solder, and the solder barrier layer of titanium material may prevent the solder from contacting the surface of the lid wafer.Type: GrantFiled: June 10, 2015Date of Patent: December 13, 2016Assignee: RAYTHEON COMPANYInventors: Roland W. Gooch, Buu Q. Diep, Adam M. Kennedy, Stephen H. Black, Thomas A. Kocian
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Publication number: 20160340179Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.Type: ApplicationFiled: August 3, 2016Publication date: November 24, 2016Inventors: Roland W. Gooch, Buu Q. Diep, Stephen H. Black, Thomas A. Kocian, Adam M. Kennedy
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Patent number: 9427776Abstract: Methods for reducing wafer bow induced by an anti-reflective coating of a cap wafer are provided. The method may utilize a shadow mask having at least one opening therein that is positioned opposite recessed regions in a cap wafer. The method may further include depositing at least one layer of an anti-reflective coating material through the shadow mask onto a planar side of a cap wafer to provide a discontinuous coating on the planar side.Type: GrantFiled: November 29, 2012Date of Patent: August 30, 2016Assignee: RAYTHEON COMPANYInventors: Roland W. Gooch, Buu Q. Diep, Stephen H. Black, Thomas A. Kocian, Adam M. Kennedy
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Patent number: 9407820Abstract: According to one aspect, embodiments herein provide a sensing device comprising an accelerometer configured to monitor acceleration of the sensing device and provide acceleration information including a value of the acceleration of the sensing device, and an Integrated Circuit (IC) coupled to the accelerometer, the IC configured to receive the acceleration information from the accelerometer and render the sensing device permanently inoperable in response to the value of the acceleration of the sensing device exceeding a threshold indicative of a military application of the sensing device.Type: GrantFiled: February 15, 2013Date of Patent: August 2, 2016Assignee: RAYTHEON COMPANYInventors: Stephen H. Black, Paolo Masini
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Publication number: 20160167959Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.Type: ApplicationFiled: February 19, 2016Publication date: June 16, 2016Applicant: Raytheon CompanyInventors: Adam M. Kennedy, Buu Q. Diep, Stephen H. Black, Tse E. Wong, Thomas Allan Kocian, Gregory D. Tracy
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Patent number: 9334154Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.Type: GrantFiled: August 11, 2014Date of Patent: May 10, 2016Assignee: RAYTHEON COMPANYInventors: Adam M. Kennedy, Buu Q. Diep, Stephen H. Black, Tse E. Wong, Thomas Allan Kocian, Gregory D. Tracy
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Patent number: 9277142Abstract: An infrared thermal imaging system includes a focal plane array (FPA) of infrared detectors, read out integrated circuitry (ROIC) operatively coupled to the FPA, and a microcontroller having at least one video display interface operatively coupled to the ROIC. The FPA is configured to generate an output signal in response to infrared radiation impinging upon the infrared detectors. The microcontroller is configured to send data to the ROIC via the at least one video display interface, the data including non-uniformity correction terms for correcting non-uniformities of the FPA.Type: GrantFiled: May 29, 2012Date of Patent: March 1, 2016Assignee: RAYTHEON COMPANYInventors: Matthew T. Kuiken, Stephen H. Black
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Publication number: 20160040282Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.Type: ApplicationFiled: October 16, 2015Publication date: February 11, 2016Applicant: RAYTHEON COMPANYInventors: Roland Gooch, Adam M. Kennedy, Stephen H. Black, Thomas Allan Kocian, Buu Diep
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Publication number: 20160039665Abstract: A sealed package having a device disposed on a wafer structure and slid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.Type: ApplicationFiled: August 11, 2014Publication date: February 11, 2016Inventors: Adam M. Kennedy, Buu Q. Diep, Stephen H. Black, Tse E. Wong, Thomas Allan Kocian, Gregory D. Tracy
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Patent number: 9227839Abstract: A structure for detecting electromagnetic radiation having a predetermined wavelength. The structure includes a device wafer having a sensing element disposed on a predetermined region of a surface of the device wafer responsive to the electromagnetic radiation. A cover wafer is provided having a region thereof transparent to the electromagnetic radiation for passing the electromagnetic radiation through the transparent region onto a surface of the sensing element. A bond gap spacer structure is provided for supporting the surface of the sensing element from an opposing surface of the transparent region of the cover wafer a distance less than a fraction of the predetermined wavelength when the cover wafer is bonded to the device wafer.Type: GrantFiled: May 6, 2014Date of Patent: January 5, 2016Assignee: RAYTHEON COMPANYInventors: Roland W. Gooch, Stephen H. Black, Thomas A. Kocian, Adam M. Kennedy, Buu Q. Diep
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Patent number: 9196556Abstract: A getter structure and method wherein a layer of seed material is deposited on a predetermined region of a surface of a structure under conditions to form a plurality of nucleation sites on a surface of the structure. The nucleation sites have an average height over the surface area of the predetermined region of less than one molecule thick. Subsequently a getter material is deposited over the surface to form a plurality of getter material members projecting outwardly from the nucleation sites.Type: GrantFiled: February 28, 2014Date of Patent: November 24, 2015Assignee: RAYTHEON COMPANYInventors: Roland Gooch, Adam M. Kennedy, Stephen H. Black, Thomas Allan Kocian, Buu Diep