Abstract: A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.

Abstract: A data processing device 100 comprises a plurality of storage circuits 130, 160, which store a plurality of data elements of the bits in an interleaved manner. Data processing device also comprises a consumer 110 with a number of lanes 120. The consumer is able to individually access each of the plurality of storage circuits 130, 160 in order to receive into the lanes 120 either a subset of the plurality of data elements or y bits of each of the plurality of data elements. The consumer 110 is also able to execute a common instruction of each of the plurality of lanes 120. The relationship of the bits is such that b is greater than y and is an integer multiple of y. Each of the plurality of storage circuits 130, 160 stores at most y bits of each of the data elements. Furthermore, each of the storage circuits 130, 160 stores at most y/b of the plurality of data elements. By carrying out the interleaving in this manner, the plurality of storage circuits 130, 160 comprise no more than b/y storage circuits.

Abstract: A data processing device 100 comprises a plurality of storage circuits 130, 160, which store a plurality of data elements of the bits in an interleaved manner. Data processing device also comprises a consumer 110 with a number of lanes 120. The consumer is able to individually access each of the plurality of storage circuits 130, 160 in order to receive into the lanes 120 either a subset of the plurality of data elements or y bits of each of the plurality of data elements. The consumer 110 is also able to execute a common instruction of each of the plurality of lanes 120. The relationship of the bits is such that b is greater than y and is an integer multiple of y. Each of the plurality of storage circuits 130, 160 stores at most y bits of each of the data elements. Furthermore, each of the storage circuits 130, 160 stores at most y/b of the plurality of data elements. By carrying out the interleaving in this manner, the plurality of storage circuits 130, 160 comprise no more than b/y storage circuits.

Abstract: A compound of formula I, and its pharmaceutically acceptable salt or salts and physiologically hydrolysable derivatives in free form or salt form: wherein either Q1, CR6a and optionally R6b together form a cyclic moiety wherein: Q1 is selected from C1-2 alkylene, C1-2 alkenylene, OC1 alkylene and OC1 alkenylene moieties optionally substituted by oxo; R6a is a single bond and R6b is H; or R6a and R6b together form a double bond; and Q2 and Q3 are independently selected from H, R1 and R2; or Q2 and Q3 together form a cyclic moiety in which one of Q2 and Q3 is a cyclic moiety selected from OC1 alkylene and OC1 alkenylene moieties optionally substituted by oxo or a group R5 as here in below defined for R2 and the other of Q2 and Q3 is a cyclic moiety selected from C1-2 alkylene, C1-2 alkenylene and OC1 alkylene optionally substituted by oxo; R6a and R6b are each H or a cyclic moiety as defined above; and Q1 is selected from H, R1 and R2 and a cyclic moiety as defined above; and R1-4 are H or substituen

Abstract: A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units.

Abstract: A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units.

Abstract: An integrated circuit includes an array of interconnected programmable logic elements (2) each logic element performing data processing control by a configuration. The logic elements may be part of a field programmable gate array. Embedded within the array are a plurality of dedicated communication interface circuits (36) providing access to one or more shared communication channels (38) to provide intra-array communication. Communication transactions between functional unit (78, 80, 82, 84) are multiplexed (e.g. time-division-multiplexed) together to share a shared communication channel provided within the array.

Abstract: A compound of formula I-0, and its pharmaceutically acceptable salt or salts and physiologically hydrolysable derivatives in free form or salt form: wherein Z1 is C1-C4 linear or branched alkyl or alkenyl; R4 is selected from unsubstituted and substituted C3-C3 cycloalkyl, C1-C8 linear or branched alkyl, C2-5 alkenyl, C6-C10 heteroaryl or aryl, or C3-C8 heterocyclyl which may be part unsaturated, and combinations thereof; Z is linear C2-3 alkylene; X1 is selected from NH and O; X2 is selected from unsaturated C and unsaturated S; and X3 is selected from NH and CH2; or one of X1 and X3 is a single bond; or X1 is O and X2 and X3 together are a single bond; and R7 is selected from oxo, F, Cl, Br, CN, NH2, NR92, NO2, CF3, OR9, COR9, OCOR9, COOR9, NR9COR9, CONR92SO2NR92, NR9SO2R9; and R8 is selected from C1-5 alkyl, C1-5 alkoxyl, C2-5 alkenyl or alkynyl, C6-10 aryl and C3-8 cycloalkyl and combinations thereof, which may be unsubstituted or further substituted by one or more F, Cl, Br, CN, NH2, NR32, NO2, CF3;

Abstract: An integrated circuit (8) comprising an array (10) of interconnected configurable logic elements (12), such as an FPGA array, is provided. The logic elements are used to form a power controller (14) which separately controls the power state of different regions of the array. Each region of the array contains one or more logic elements. Each region has a corresponding region controller (16) responsive to one or more power signals generated by the power controller to switch that region into the requested power state.

Abstract: A high content screening (HCS) assay for rapidly screening one or more compounds to determine functional response or pharmacological properties thereof, comprising: i) priming a cell or cell material with a sensor for a biological response; ii) contacting the compound(s) to be tested with the primed cell or cell material or contacting a cell or cell material which has been contacted with the compound(s) with the primed cell or cell material; iii) simultaneously or subsequently contacting with a fluorescent agonist or a fluorescent neutral antagonist wherein the binding of the fluorescent agonist or antagonist and its associated biological response are detected or monitored in the same cell and are distinct allowing separate readout.

Abstract: An observation cell arrangement for flow perfusion of a sample to be examined, the arrangement comprising a flow cell (21) having a cavity therein to receive the sample, the flow cell (21) arranged to receive a flow of fluid through the cavity that is directed over the sample from a cavity inlet (22) to a cavity outlet (23), the cavity inlet (22) associated with a fluid supply line, and a first flow supply path (24) connected to the fluid supply line via a valve (39), the first flow supply path (24) adapted to receive pressure from a pressure source comprising a pressure reservoir (29) to drive fluid flow through the cavity at a desired flow rate

Abstract: A method for generating a recombinant clonal cell line expressing a target cell surface receptor at a specific level of expression from a cell population comprising cells transfected with a plasmid encoding the cDNA sequence of the target receptor and expressing the target cell surface receptor, the method comprising (c) incubating the cell population with a receptor specific fluorescent ligand (d) selecting single cells from step (c) expressing the target cell surface receptor by monitoring the specific binding of the fluorescent ligand using flow cytometry; and novel fluorescent ligands.

Abstract: A data processing apparatus is provided comprising first processing circuitry, second processing circuitry and shared processing circuitry. The first processing circuitry and second processing circuitry are configured to operate in different first and second power domains respectively and the shared processing circuitry is configured to operate in a shared power domain. The data processing apparatus forms a uni-processing environment for executing a single instruction stream in which either the first processing circuitry and the shared processing circuitry operate together to execute the instruction stream or the second processing circuitry and the shared processing circuitry operate together to execute the single instruction stream. Execution flow transfer circuitry is provided for transferring at least one bit of processing-state restoration information between the two hybrid processing units.

Abstract: An integrated circuit includes an array of interconnected programmable logic elements (2) each logic element performing data processing control by a configuration. The logic elements may be part of a field programmable gate array. Embedded within the array are a plurality of dedicated communication interface circuits (36) providing access to one or more shared communication channels (38) to provide intra-array communication. Communication transactions between functional unit (78, 80, 82, 84) are multiplexed (e.g. time-division-multiplexed) together to share a shared communication channel provided within the array.

Abstract: An integrated circuit (8) comprising an array (10) of interconnected configurable logic elements (12), such as an FPGA array, is provided. The logic elements are used to form a power controller (14) which separately controls the power state of different regions of the array. Each region of the array contains one or more logic elements. Each region has a corresponding region controller (16) responsive to one or more power signals generated by the power controller to switch that region into the requested power state.

Abstract: A data processing apparatus comprising a processor for executing a data processing process and a processor for executing a tuning process is disclosed. The data processing apparatus is arranged such that the tuning process which is a different process to the data processing process can access the parameters of speculative mechanisms of the data processing process and tune the parameters so that the mechanisms speculate differently and in this way the performance of this data processing process can be improved.

Abstract: A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each decode unit being operable to only decode the remaining set of instructions from a corresponding one of the plurality of instruction sets; and a common decode unit operable to decode a number of the sub-set of common instructions from each of the plurality of instruction sets. This enables the common instructions from each instruction set to be decoded by the common decode unit. Hence, the logic which would otherwise be duplicated in each of the individual decode units for each instruction set can be removed from those decode units and provided just once in the common decode unit.

Abstract: A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.

Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.

Abstract: A blade server 2 is provided with a processor 6 for executing program instructions and an electrical connector 12 for connecting to a blade enclosure 22. The blade server 2 also includes a power controller 18 connected to a plurality of power supply batteries 14, 16 which are provided on the blade server 2 itself. If the power controller 18 detects that the main power supply supplied via the electrical connector 12 has been interrupted, then a backup power supply to the processor is provided from the on-board power supply batteries 14, 16. The batteries 14, 16 on each blade are periodically discharged and recharged in turn to check their proper function.