Patents by Inventor Stephen John Hill
Stephen John Hill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7831815Abstract: A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of instructions is identified, the equivalent accelerator instruction is stored in the cache structure as a replacement for the first instruction of the sequence, with the remaining instructions in the sequence of instructions being stored unchanged. The accelerator instruction includes an indication to cause the processing unit to skip the remainder of the sequence when executing the accelerator instruction.Type: GrantFiled: February 6, 2008Date of Patent: November 9, 2010Assignee: ARM LimitedInventors: Peter Richard Greenhalgh, Stephen John Hill
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Patent number: 7802080Abstract: A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception handler.Type: GrantFiled: March 24, 2004Date of Patent: September 21, 2010Assignee: ARM LimitedInventors: David John Butcher, Stephen John Hill, Hedley James Francis, Vladimir Vasekin, Andrew Christopher Rose
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Patent number: 7774582Abstract: A data processing system including multiple execution pipelines each having multiple execution stages E1, E2, E3 may have instructions issued together in parallel despite a data dependency therebetween if it is detected that the result operand value for the older instruction will be generated in an execution stage prior to an execution stage which requires that result operand value as an input operand value to the younger instruction and accordingly cross-forwarding of the operand value is possible between the execution pipelines to resolve the data dependency.Type: GrantFiled: May 26, 2005Date of Patent: August 10, 2010Assignee: ARM LimitedInventors: David James Williamson, Glen Andrew Harris, Stephen John Hill
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Publication number: 20100100704Abstract: An integrated circuit 4 is provided including an array 10 of processors 26 with interface circuitry 12 providing communication with further processing circuitry 14. The processors 26 within the array 10 execute individual programs which together provide the functionality of a cycle-based program. During each program-cycle of the cycle based program, each of the processors executes its respective program starting from a predetermined execution start point to evaluate a next state of at least some of the state variables of the cycle-based program. A boundary between program-cycles provides a synchronisation time (point) for processing operations performed by the array.Type: ApplicationFiled: October 14, 2009Publication date: April 22, 2010Applicant: ARM LimitedInventors: Stephen John Hill, Michael Peter Muller
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Patent number: 7657694Abstract: A data processing apparatus is provided comprising processing logic for issuing access requests when access to data is required, with each access request specifying a memory address associated with the data the subject of the access request. Access control logic is used to perform an access control operation to check for each access request whether the specified memory address is accessible by the processing logic. Further, a table is provided having a plurality of entries, each entry identifying an address range and an associated action. On occurrence of one or more predetermined events, the access control logic references the table to determine whether the specified address is within the address range identified by an entry of the table. If so, the associated action specified in that entry is invoked, whereas otherwise the access control logic causes any action indicated by the access control operation to be performed.Type: GrantFiled: December 20, 2006Date of Patent: February 2, 2010Assignee: ARM LimitedInventors: David Hennah Mansell, Stuart David Biles, Stephen John Hill
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Publication number: 20090198978Abstract: A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of instructions is identified, the equivalent accelerator instruction is stored in the cache structure as a replacement for the first instruction of the sequence, with the remaining instructions in the sequence of instructions being stored unchanged. The accelerator instruction includes an indication to cause the processing unit to skip the remainder of the sequence when executing the accelerator instruction.Type: ApplicationFiled: February 6, 2008Publication date: August 6, 2009Applicant: ARM LimitedInventors: Peter Richard Greenhalgh, Stephen John Hill
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Publication number: 20090093001Abstract: A high content screening (HCS) assay for rapidly screening one or more compounds to determine functional response or pharmacological properties thereof, comprising: i) priming a cell or cell material with a sensor for a biological response; ii) contacting the compound(s) to be tested with the primed cell or cell material or contacting a cell or cell material which has been contacted with the compound(s) with the primed cell or cell material; iii) simultaneously or subsequently contacting with a fluorescent agonist or a fluorescent neutral antagonist wherein the binding of the fluorescent agonist or antagonist and its associated biological response are detected or monitored in the same cell and are distinct allowing separate readout.Type: ApplicationFiled: September 26, 2005Publication date: April 9, 2009Inventors: Stephen John Hill, Barrie Kellam, Stephen John Briddon
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Patent number: 7496899Abstract: Techniques for preventing the loss of trace information being transmitted via trace infrastructure are disclosed. A data processing apparatus for processing instructions is provided.Type: GrantFiled: August 17, 2005Date of Patent: February 24, 2009Assignee: ARM LimitedInventors: Stephen John Hill, Glen Andrew Harris, David James Williamson
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Publication number: 20090015322Abstract: An integrated circuit 78 is formed of multiple layers of circuits 14, 16 superimposed to produce stacks of circuit blocks 2, 4. Stack control circuitry 18, 20 is associated with the input and output signals from the circuit blocks to direct these to/from the currently active circuit block(s) as appropriate. The superimposed circuit blocks 2, 4 provide redundancy for each other, both for manufacturing defect resistance and for operational redundancy, such as providing multiple modular redundancy in safety critical environments.Type: ApplicationFiled: January 10, 2008Publication date: January 15, 2009Applicant: ARM LimitedInventors: Krisztian Flautner, Robert Campbell Aitken, Stephen John Hill
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Publication number: 20080155167Abstract: A data processing apparatus is provided comprising processing logic for issuing access requests when access to data is required, with each access request specifying a memory address associated with the data the subject of the access request. Access control logic is used to perform an access control operation to check for each access request whether the specified memory address is accessible by the processing logic. Further, a table is provided having a plurality of entries, each entry identifying an address range and an associated action. On occurrence of one or more predetermined events, the access control logic references the table to determine whether the specified address is within the address range identified by an entry of the table. If so, the associated action specified in that entry is invoked, whereas otherwise the access control logic causes any action indicated by the access control operation to be performed.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Inventors: David Hennah Mansell, Stuart David Biles, Stephen John Hill
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Patent number: 7389459Abstract: A data processing apparatus is provided having a plurality of functional units. At least one of the functional units is operable to perform data processing operations and at least a subset of the plurality of functional units have at least one of a respective co-processor register for storing configuration data and a respective debug register for storing debug data. A debug controller outputs debug data and co-ordinates debug operations. A configuration ring-bus provides a ring path for communication of configuration instructions between a first ring sequence of the plurality of functional units and a debug ring-bus provides a ring path for communication of the debug data between a second ring sequence of the plurality of functional units. Separate provision of the debug ring-bus and the configuration ring-bus provides independent access to the co-processor register and to the debug register.Type: GrantFiled: March 22, 2005Date of Patent: June 17, 2008Assignee: ARM LimitedInventors: Conrado Blasco Allue, Stephen John Hill, David James Williamson
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Patent number: 7293212Abstract: A data processing apparatus is operable in a either a self-test mode or an operational mode. The apparatus comprises a plurality of functional units, at least one of the functional units being operable to perform data processing operations and at least a subset of the plurality of functional units having at least one of a respective co-processor register for storing configuration data, a respective debug register for storing debug data and a respective functional unit memory. A memory self-test controller operable in the self-test mode to output self-test data for performing access operations to confirm correct operation of the functional unit memory. A debug controller outputs debug data and co-ordinates debug operations, the debug controller being one of the plurality of functional units.Type: GrantFiled: March 22, 2005Date of Patent: November 6, 2007Assignee: ARM LimtedInventors: Conrado Blasco Allue, Stephen John Hill, Richard Slobodnik
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Patent number: 7269766Abstract: A self-test controller 10 is responsive to scanned in self-test instructions to carry out test operations including generating a sequence of memory addresses that is specified by the self-test instruction. Combining multiple such self-test instructions allows a custom test methodology to be built up by a user using a generic self-test controller 10.Type: GrantFiled: December 26, 2001Date of Patent: September 11, 2007Assignee: ARM LimitedInventors: Richard Slobodnik, Stephen John Hill, Gerard Richard Williams
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Patent number: 7234043Abstract: Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then be used to correct any decoding which has been performed upon the basis of an assumption that the program instructions are predicated. The predication instruction can predicate a variable number of following instructions. The predication instruction can issue in parallel with an instruction which it predicates and yet the proper identification of the predication instruction need not be confirmed until at least some decoding has been performed upon the other program instruction.Type: GrantFiled: March 7, 2005Date of Patent: June 19, 2007Assignee: ARM LimitedInventors: Conrado Blasco Allue, Glen Andrew Harris, Stephen John Hill
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Patent number: 7174472Abstract: An integrated circuit provided with a power down and power up mechanism which operates by storing state data including at least architectural state data within storage cells having their own power supply with the main power supply being removed during the power down mode. Prior to removing the main power supply execution of data processing instructions within the instruction pipeline preceding a restart instruction are completed so as to reduce the amount of state data which needs to be stored across the power down event. Thus, a compromise is achieved between rapid power down through the use of dedicated storage cells and the circuit area requirements of such storage cells and the need to complete execution of some partially executed data processor instructions within the instruction pipeline and other operations such as, pending writes within the integrated circuit.Type: GrantFiled: May 20, 2003Date of Patent: February 6, 2007Assignee: Arm LimitedInventor: Stephen John Hill
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Patent number: 6990569Abstract: A data processing apparatus is provided comprising: a processor operable to execute instructions, each instruction having a micro-architectural state information associated therewith; comparator logic operable to compare the micro-architectural state information with predetermined micro-architectural state information associated with a problematic event and to issue a match signal if a match is detected; and trigger logic responsive to the match signal to provide one of a plurality of output signals, the trigger logic being programmable to determine which of the output signals is provided upon receipt of the match signal, each output signal being arranged to activate a corresponding mechanism to handle the problematic event. This advantageous arrangement alleviates problems encountered by prior art approaches by providing a programmable mechanism to identify a problematic event and to activate an appropriate mechanism to handle that problematic event.Type: GrantFiled: October 25, 2001Date of Patent: January 24, 2006Assignee: Arm LimitedInventor: Stephen John Hill
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Publication number: 20040236968Abstract: An integrated circuit 2 is provided with a power down and power up mechanism which operates by storing state data including at least architectural state data within storage cells having their own power supply with the main power supply being removed during the power down mode. Prior to removing the main power supply execution of data processing instructions within the instruction pipeline 14 proceeding a restart instruction is completed so as to reduce the amount of state data which needs to be stored across the power down event. Thus, a compromise is achieved between rapid power down mode entry through the use of dedicated storage cells and the circuit area requirements of such storage cells, this being traded against the need to complete execution of some partially executed data processor instructions within the instruction pipeline 14 and other operations such as, pending write within the integrated circuit 2.Type: ApplicationFiled: May 20, 2003Publication date: November 25, 2004Applicant: ARM LIMITEDInventor: Stephen John Hill
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Publication number: 20030120985Abstract: A self-test controller 10 is responsive to scanned in self-test instructions to carry out test operations including generating a sequence of memory addresses that is specified by the self-test instruction. Combining multiple such self-test instructions allows a custom test methodology to be built up by a user using a generic self-test controller 10.Type: ApplicationFiled: December 26, 2001Publication date: June 26, 2003Inventors: Richard Slobodnik, Stephen John Hill, Gerard Richard Williams
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Publication number: 20030084272Abstract: A data processing apparatus is provided comprising: a processor operable to execute instructions, each instruction having a micro-architectural state information associated therewith; comparator logic operable to compare the micro-architectural state information with predetermined micro-architectural state information associated with a problematic event and to issue a match signal if a match is detected; and trigger logic responsive to the match signal to provide one of a plurality of output signals, the trigger logic being programmable to determine which of the output signals is provided upon receipt of the match signal, each output signal being arranged to activate a corresponding mechanism to handle the problematic event. This advantageous arrangement alleviates problems encountered by prior art approaches by providing a programmable mechanism to identify a problematic event and to activate an appropriate mechanism to handle that problematic event.Type: ApplicationFiled: October 25, 2001Publication date: May 1, 2003Inventor: Stephen John Hill
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Patent number: 6550005Abstract: Apparatus (5) and method for processing data in response to a sequence of program instructions including a primary pipelined processing unit (40) for performing data processing, the primary pipelined processing unit being responsive to a cancellation condition such as an abort to cancel processing of a partially completed program instruction. The apparatus and method comprising a pseudo instruction generator (30) to generate a pseudo instruction to a fix-up pipelined processing unit (50) in response to a program instruction (LDM, STM) that can be subject to cancellation, the pseudo instruction controlling the fix-up pipelined processing unit to produce a state in which the partially completed program instruction may be re-executed at a later time.Type: GrantFiled: November 29, 1999Date of Patent: April 15, 2003Assignee: Arm LimitedInventor: Stephen John Hill