Abstract: An apparatus and method is provided for determining locations of a predetermined value in a sequence of data bits. Each location is determined independently of the others thereby allowing them to be found more quickly. This has particular application to block memory loads and block stores to memory, wherein ones in the register list in the instruction word indicate the registers to be loaded or stored. Thus, in these applications the present invention enables the positions of these ones to be determined quickly.

Abstract: The present invention provides a voltage level shifter for use in a digital circuit having a low voltage portion and a high voltage portion. The voltage shifter comprises an interface circuit 20,32,60 that senses transitions in a low voltage digital signal from an old value to a new value and uses these to trigger latching of the new value. The latch can be a SR latch 34,62 with its set 40 and reset 42 inputs coupled to pulse generators 46,68,58,70 respectively responsive to rising and falling edges in the input low voltage signal being passed from the low voltage portion to the high voltage portion. Feedback from the output on the latch 62 can be controlled to limit the duration of the pulses from the pulse generators 68,70 and thereby reduce power consumption due to the dc current leakage associated with a low voltage to high voltage signal interface.

Abstract: A data processing apparatus is provided comprising a processor core for performing processing operations, and a register bank comprising a plurality of registers for storing data values used by the processor core, the register bank having first and second portions such that in preferred embodiments the first portion of the register bank may be arranged to include the more frequently accessed registers. Each register in the register bank comprises a plurality of memory cells for storing data bits, and the register bank has a bit line associated with corresponding memory cells from a number of said registers, each memory cell being arranged, upon receipt of a command, to selectively alter the associated bit line from a first state to a second state dependent on the data bit stored in that memory cell.

Abstract: The present invention provides an output buffer 38 for the signal from a bit line 16 that is precharged by a precharging gate 34. The output buffer 38 comprises a stack of field effect transistors made up of an isolation transistor 40 switched by a clock signal indicating the precharge period, a precharge state driver transistor 42 and a non-precharge state driver transistor 44. The non-precharge state driver transistor 44 is connected directly between the output signal line of the output buffer and the ground. The two driver transistors 42,44 are of different polarities and are switched by the bit line signal. In operation, during the precharge period, the precharge state driver transistor 42 is disabled from changing the output of the output buffer 38 by the isolation transistor 40 whilst the non-precharge state driver transistor 44 is disabled by the transition to or maintenance of the precharge signal value on the bit line 16.