Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.

Abstract: A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.

Abstract: A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses.

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: A drive circuit includes drive input and output terminals, a supply terminal, a drive transistor, and a drive-control circuit. The drive transistor includes a control terminal, a first transistor terminal coupled to the drive output terminal, and a second transistor terminal coupled to the supply terminal. The drive-control circuit has an input terminal coupled to the drive input terminal and has an output terminal coupled to the control terminal of the drive transistor. The drive-control circuit generates on the control terminal of the drive transistor a signal level that changes at a first rate during a first time period and at a second higher rate during a second time period following the first time period. As a result, when used as a data-output driver, one can adjust the first and second rates and time periods such that the drive circuit meets both the 50-ohm and 50 pf falling-slew-rate ranges specified in the Intel® PC-100 specification.