Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: A cell margin test method for a dynamic cell plate sensing (DCPS) memory array. In a DCPS memory array, voltage moves on both a digitline and a cell plate line associated with an accessed memory cell. Voltage movement on the digitline and its associated cell plate line is in opposite directions, i.e., voltage on one line moves up (goes high) and voltage on the other line moves down (goes low). Because voltage movement is in opposite directions, this produces a voltage swing which is larger than that produced by a conventional digitline pair approach, in which one digitline remains at a reference potential and the other digitline moves away from the reference potential. A method is provided for a DCPS memory array which tests sense amplifier latching with a voltage swing produced with one line (either a digitline or a cell plate line) held at a reference potential and another line (either a digitline or a cell plate line) moved away from the reference potential.

Abstract: A voltage generator coupled to a capacitor is provided. In one embodiment, the voltage generator includes an input that receives a control signal that indicates a desired current level output, and further includes circuitry adapted to generate a selected voltage, activate a first current path for an output of the voltage generator when a first current level is desired, and activate a second current path for the output of the voltage generator when a second current level is desired.

Abstract: An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

Abstract: A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

Abstract: An internal voltage regulator for a synchronous random access memory (“SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.

Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.

Abstract: An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two states having a first and second current draw, respectively. The smoothing circuit also has a first and second state and a first and second current draw, respectively. The current draws of the primary circuit and the smoothing circuit are such that the total current draw on the voltage source through the inductive conductor maintains relatively constant regardless of the state that the primary circuit is in, thus minimizing any induced voltage transients as a result of the conductor's inductance.

Abstract: An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two states having a first and second current draw, respectively. The smoothing circuit also has a first and second state and a first and second current draw, respectively. The current draws of the primary circuit and the smoothing circuit are such that the total current draw on the voltage source through the inductive conductor maintains relatively constant regardless of the state that the primary circuit is in, thus minimizing any induced voltage transients as a result of the conductor's inductance.

Abstract: A method for testing a memory device. The method writes test data to an array of cells of the memory device during a test mode. The method calls for driving a cell plate of the memory device during at least a portion of the test with a current level that is less than the current used during normal operation. This amplifies the affect of defective cells on the cell plate voltage thereby allowing identification of unacceptably weak cells with shorter, less strenuous tests.

Abstract: A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

Abstract: An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

Abstract: An integrated circuit voltage regulator compensates for temperature variations by adjusting a gain of an amplifier. In one embodiment, the gain is controlled by a voltage divider circuit comprised of a first resistor having a first temperature coefficient, and a second resistor having a second temperature coefficient which is different from the first coefficient. In one embodiment, the first resistor is a p-channel transistor and the second resistance is fabricated from integrated circuit active area.

Abstract: An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. In another embodiment, the tri-state input stage includes series coupled pairs of N and P channel transistors. The address signal is provided to gates of one P channel and one N channel transistor which form an inverter. The other two transistors have their gates coupled to the address enable signal and its complement for enabling the tri-state input stage. In another embodiment, the address output latch includes a multiplexed feedback loop that is controlled by the address enable signal and its complement. A method of operating the buffer comprises sampling a signal. The sampled signal is inverted. The inverted sampled signal is latched. Finally, the latched signal is inverted.

Abstract: A method for testing a memory device. The method writes test data to an array of cells of the memory device during a test mode. The method calls for driving a cell plate of the memory device during at least a portion of the test with a current level that is less than the current used during normal operation. This amplifies the affect of defective cells on the cell plate voltage thereby allowing identification of unacceptably weak cells with shorter, less strenuous tests.

Abstract: An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. In another embodiment, the tri-state input stage includes series coupled pairs of N and P channel transistors. The address signal is provided to gates of one P channel and one N channel transistor which form an inverter. The other two transistors have their gates coupled to the address enable signal and its complement for enabling the tri-state input stage. In another embodiment, the address output latch includes a multiplexed feedback loop that is controlled by the address enable signal and its complement. A method of operating the buffer comprises sampling a signal. The sampled signal is inverted. The inverted sampled signal is latched. Finally, the latched signal is inverted.

Abstract: An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two states having a first and second current draw, respectively. The smoothing circuit also has a first and second state and a first and second current draw, respectively. The current draws of the primary circuit and the smoothing circuit are such that the total current draw on the voltage source through the inductive conductor maintains relatively constant regardless of the state that the primary circuit is in, thus minimizing any induced voltage transients as a result of the conductor's inductance.

Abstract: A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.

Abstract: A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

Abstract: An internal voltage regulator for a synchronous random access memory (“SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.