Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

Abstract: A memory device is described which is fabricated as an integrated circuit and uses distributed bond pads for electrical connection to an external conductive lead. The distributed bond pads are attached to a external lead, thereby eliminating bus lines on the integrated circuit memory. Distributed buffer circuits are described which can be included with the distributed bond pads to increase data communication time between the memory device and an external processor.

Abstract: The provision of an isolation gate connecting unassociated active areas of adjacent transistors formed in a semiconductor substrate provides effective isolation of the adjacent transistors with no additional process steps required. The isolation gate is tied to a reference to ensure that a channel between the unassociated active areas is not formed, and effective isolation is provided. The adjacent transistors are cross coupled to form sense amplifiers for dynamic random access memory devices.

Abstract: A method for storing a temperature threshold in an integrated circuit includes measuring operating parameters of the integrated circuit versus temperature, calculating a maximum temperature at which the integrated circuit performance exceeds predetermined specifications and storing parameters corresponding to the maximum temperature in a comparison circuit in the integrated circuit by selectively blowing fusable devices in the comparison circuit. The fusable devices may be antifuses. As a result, the integrated circuit is able to provide signals to devices external to the integrated circuit to indicate that the integrated circuit may be too hot to operate properly.

Abstract: A memory device. The memory device includes an array of memory cells that are coupled to a number of word lines and a number of digit lines. The memory device further includes an addressing circuit that is coupled to the array. The addressing circuit selects a memory cell based on a received address signal. An input/output device is coupled to the digit lines of the array. The input/output device includes an input for receiving a control signal. A control circuit is coupled to the input of the input/output device. The control circuit produces a control signal with a first voltage level when reading data from the array and produces a control signal with a second voltage level when writing data to the array. Thus, the control signal causes the input/output device to provide acceptable drive current during a read operation such that the input/output device does not disturb the data on the digit lines.

Abstract: An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two states having a first and second current draw, respectively. The smoothing circuit also has a first and second state and a first and second current draw, respectively. The current draws of the primary circuit and the smoothing circuit are such that the total current draw on the voltage source through the inductive conductor maintains relatively constant regardless of the state that the primary circuit is in, thus minimizing any induced voltage transients as a result of the conductor's inductance.

Abstract: An internal voltage regulator for a synchronous random access memory “SDRAM”) uses a regulator circuit to supply power to charge pumps that is separate from a regulator circuit that supplies power to the arrays of the SDRAM. The regulator supplies an output voltage to the charge pumps that is maintained constant as the external supply voltage is increased beyond its normal operating range. In contrast, a regulated circuit that supplies power to the arrays increases as the supply voltage is increase beyond its normal operating range. As a result, the voltage regulator allows the arrays to be stress tested with a relatively high regulated output voltage without applying an excessive and potentially damaging regulated output voltage to the charge pumps.

Abstract: A memory device is described which is fabricated as an integrated circuit and uses distributed bond pads for electrical connection to an external conductive lead. The distributed bond pads are attached to a external lead, thereby eliminating bus lines on the integrated circuit memory. Distributed buffer circuits are described which can be included with the distributed bond pads to increase data communication time between the memory device and an external processor.

Abstract: An antifuse detection circuit is described which uses a latching circuit and two antifuses. The antifuses are coupled between the latch circuit and ground. The latching circuit described is a differential circuit which can detect which one of the two antifuses has been programmed. The circuit accurately detects an antifuse which has a relatively high resistance after being programmed.

Abstract: A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

Abstract: An address buffer for a memory device comprises a tri-state input stage, an address output latch, and an inverter that are successively coupled. In one embodiment, the address buffer uses address enable signals for controlling both the tri-state input stage and the address output latch. In another embodiment, the tri-state input stage includes series coupled pairs of N and P channel transistors. The address signal is provided to gates of one P channel and one N channel transistor which form an inverter. The other two transistors have their gates coupled to the address enable signal and its complement for enabling the tri-state input stage. In another embodiment, the address output latch includes a multiplexed feedback loop that is controlled by the address enable signal and its complement. A method of operating the buffer comprises sampling a signal. The sampled signal is inverted. The inverted sampled signal is latched. Finally, the latched signal is inverted.

Abstract: A method of operating a sense amplifier comprises floating an isolation gate line signal when a memory cell is being accessed. In one embodiment, the isolation gate is first turned on by biasing the gate line of the isolation gate. Then, the input of a sense amplifier is coupled to a desired memory cell and about the same time, the isolation gate is floated. The isolation gate is at least partially turned off by a reduction in the voltage level of the ISO gateline through capacitance based decay. This at least partially isolates other memory cells and/or circuitry accessed through a set of digit lines, allowing the sense amplifier to more easily sense the state of the desired memory cell. The isolation gate is floated by coupling the gate line of the isolation gate to a high impedance. The sense amplifier may be an N-sense amplifier. The isolation gate is floated prior to sense amplifier being activated.

Abstract: A cell margin test method for a dynamic cell plate sensing (DCPS) memory array. In a DCPS memory array, voltage moves on both a digitline and a cell plate line associated with an accessed memory cell. Voltage movement on the digitline and its associated cell plate line is in opposite directions, ie., voltage on one line moves up (goes high) and voltage on the other line moves down (goes low). Because voltage movement is in opposite directions, this produces a voltage swing which is larger than that produced by a conventional digitline pair approach, in which one digitline remains at a reference potential and the other digitline moves away from the reference potential. A method is provided for a DCPS memory array which tests sense amplifier latching with a voltage swing produced with one line (either a digitline or a cell plate line) held at a reference potential and another line (either a digitline or a cell plate line) moved away from the reference potential.

Abstract: A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.

Abstract: A method for testing a memory device. The method writes test data to an array of cells of the memory device during a test mode. The method calls for driving a cell plate of the memory device during at least a portion of the test with a current level that is less than the current used during normal operation. This amplifies the affect of defective cells on the cell plate voltage thereby allowing identification of unacceptably weak cells with shorter, less strenuous tests.

Abstract: An attenuating circuit for reducing the inductively induced voltage transients in an electrical signal. The attenuating circuit is formed by a primary circuit and a smoothing circuit both coupled to a voltage source through an inductive conductor. The primary circuit operates in two states having a first and second current draw, respectively. The smoothing circuit also has a first and second state and a first and second current draw, respectively. The current draws of the primary circuit and the smoothing circuit are such that the total current draw on the voltage source through the inductive conductor maintains relatively constant regardless of the state that the primary circuit is in, thus minimizing any induced voltage transients as a result of the conductor's inductance.

Abstract: A multilayer decoupling capacitor structure is disclosed, having a first decoupling capacitor with one electrode formed in a conductively doped silicon substrate and a second electrode made of conductively doped polysilicon. A third bifurcated conductive layer disposed above the second electrode in conjunction with a fourth conductive layer above the third layer form a second and third decoupling capacitor. The first decoupling capacitor serves to decouple circuitry associated with dynamic random access memory cells, while the second and third decoupling capacitors provide decoupling for further circuitry.

Abstract: A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit. The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

Abstract: A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.

Abstract: A voltage regulator circuit for regulating an input voltage supply. The voltage regulator includes an n-channel transistor that has a gate and a source/drain region. The source/drain region of the transistor provides an output signal for the regulator circuit. The regulator circuit also includes a pull-up device that is coupled between a pumped voltage supply and a gate of the n-channel transistor. A pull-down device is also coupled between the gate of the n-channel transistor and ground potential. The voltage regulator also includes a level sensing circuit that is responsive to the gate of the n-channel transistor. The level sensing circuit generates a control signal for a control input of the pull-down device to provide feedback control of the n-channel transistor to regulate the output of the source/drain of the n-channel transistor.