Abstract: A monolithic clamping circuit (10) and a method of protecting a semiconductor power transistor (14) from entering avalanche breakdown. The semiconductor power transistor (14) controls the switching of an inductor (16). The monolithic clamping circuit (10) causes energy stored in the inductor (16) to be dissipated in the semiconductor power transistor (14). A voltage sense circuit (18) provides a feedback signal to a selector circuit (12) in response to a voltage at a collector terminal of the semiconductor power transistor (14). The selector circuit (12) switches the semiconductor power transistor (14) to the conductive mode when the feedback signal indicates a high voltage at the collector terminal of the semiconductor power transistor (14). Dissipating the energy stored in the inductor (16) while operating in the conductive mode prevents the semiconductor power transistor (14) from entering avalanche breakdown.

Abstract: A semiconductor device includes a substrate (11), a first region (21) in the substrate (11) wherein the first region (21) has a first conductivity type, a second region (22) in the substrate (11) wherein the second region (22) is adjacent to the first region (21) and wherein the second region (22) has a second conductivity type different from the first conductivity type, and a third region (24) in the substrate (11) wherein the third region (24) overlaps the first and second regions (21, 22) and wherein the third region (24) has a damaged crystalline structure.

Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

Abstract: A method of forming an alloyed drain field effect transistor (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: A semiconductor device is presented having an improved high voltage protection scheme that comprises an integrated Schottky diode (28) in conjunction with a plurality of back to back diodes (29) to limit a voltage potential that may arise between the gate (26) and drain terminals (27) of a semiconductor device. A second embodiment comprises a contact region (43) connected to a plurality of back to back diodes (46) configured so that some of the voltage is supported by the back to back diodes (46) and the remainder is supported by the substrate (39). These structures will support any excess voltage in the conduction mode, rather than the avalanche mode and may employ the use of a depletion region (51) to support a blocking voltage.

Abstract: An integrated turn-off circuit rapidly turns off a power transistor (14) which saves power by reducing the power dissipated while the power transistor transitions from an on-state to an off state. During an enable cycle a first coupling circuit (19) couples an enabling signal to a gate of a power transistor (14). The enabling signal charges an input capacitance to a voltage that enables the power transistor (14). A first transistor (21) for discharging the input capacitance is disabled by a second transistor (23) during the enable cycle. During a disable cycle the first coupling circuit (19) decouples the gate of the power transistor (14) from a disabling signal. The disabling signal disables the second transistor (23). A second coupling circuit (22) couples a voltage to the first transistor (21) for enabling the first transistor (21) to discharge the input capacitance and disable the power transistor.

Abstract: A transistor (200) comprises a single, common base region (202). One or more source regions (112) are formed in the base region (202). One or more gate regions (120) overly the common base (202) and the source regions (112). In an alternate embodiment, the gate regions (320) have a raised central portion (321). In yet another embodiment, certain source regions (402) are cross connected (404). Additionally, a polysilicon pattern (602) may be used which provides a gate finger feed network (614, 616, 618), and gate fingers (604, 606, 608, 620) having length less than one half of the longest die dimension.

Abstract: A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

Abstract: A semiconductor structure having an edge termination feature wherein at least one guard ring is disposed in a substrate between a main device portion and the edge of the substrate. A dielectric layer is then disposed on the substrate and a plurality of diodes are disposed on the dielectric layer above the at least one guard ring. The at least one guard ring and the diodes are electrically coupled so that the potential of the guard rings may be fixed by the diodes and leakage is greatly reduced.

Abstract: A method for fabricating a dual gate thin film transistor using a power MOSFET process having a first gate area (22) made from a monocrystalline silicon. A dielectric layer (25) is formed over the monocrystalline silicon. A first gate electrode (58) contacts the first gate area (22). A thin film transistor is fabricated on a first island of polysilicon (29) over the dielectric layer (25). The thin film transistor has a second gate electrode (55), and drain and source electrodes (56, 57) wherein the drain and source electrodes (56, 57) contact different portions of the first island of polysilicon (29). Preferably, the first gate electrode (58) is coupled to the second gate electrode (55).

Abstract: A protection circuit for providing short-circuit protection for a field effect transistor has been provided. The protection circuit senses when the voltage appearing at the gate and drain electrodes of the field effect transistor are both at a logic high voltage level, and responds to turn off the field effect transistor thereby preventing damage to the field effect transistor.

Abstract: A transient protection circuit provides protection from high voltage transients appearing along a transmission line by sensing a predetermined threshold of the voltage developed thereon and opening the conduction path through first and second switching circuits in the transmission line. The switching circuits are implemented with first and second serially coupled transistors sharing a common drain and enabled by a control signal during normal operation. The first and second transistors each have a diode oriented to conduct from the source to the drain for bi-directional operation. During high voltage transient conditions, a sensing circuit detect a predetermined threshold of the potential on the transmission line and disables one of the first and second transistors which opens the conduction path through the first and second switching circuits thereby suppressing the surge currents flowing therethrough.

Abstract: An insulated gate bipolar device is formed on a multiple conductivity substrate. The multiple conductivity substrate comprises interspersed regions of N+ and P+ semiconductor material. In a preferred embodiment, the N+ and P+ regions are arranged in a checkerboard, mosaic pattern on a bottom side of the substrate. The P+ region serves to conductivity modulate an N epitaxial layer in which the IGBT structure is formed while the N+ regions improve low current conductivity, reduce minority carrier recombination time, and make an integral drain source diode accessible from the drain and source electrodes.

Abstract: A protective circuit for an input to a bipolar transistor (10) capable of operating in the microwave frequency range. In a first embodiment, a polysilicon diode (24) is connected across a base-emitter junction of the bipolar transistor (10). In a second embodiment, a polysilicon resistor (38) is connected in series with an emitter of the bipolar transistor (10), and the polysilicon diode (24) is connected across the series combination of the base-emitter junction and the polysilicon resistor (38). The layout of the transistor (10) and the islands of polysilicon (23, 25) housing the diode is critical since the bipolar transistor (10) is capable of operating in the microwave frequency range. In a first layout, an island of polysilicon (25) is centered between two transistor regions (47 and 48). In an exterior diode layout, a transistor region (51) is centered between two islands of polysilicon (23 and 25).

Abstract: FET protection circuit (10; 100) senses the temperature of a FET (11) and, via a control circuit (24), increases FET conduction in response to sensed FET temperature exceeding a high temperature threshold (160.degree. C.) close to the maximum rated junction temperature (175.degree. C.) of the FET. This allows the FET to survive excessive drain-to-source voltages which occur during load dump conditions even when load dump is sensed by a zener diode (26) which initially turns on the FET. During load dump after a zener diode (26) turns on the FET, in response to sensing excessive FET temperature the FET is turned in harder so as to reduce the drain-to-source voltage (V.sub.DS) and minimize power dissipation during load dump thereby protecting the FET. Normal overcurrent and maximum temperture turn off circuitry (44, 33, 60-63) is effectively overridden by high temperature threshold turn-on circuitry (50).

Abstract: A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is coupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

Abstract: MOSFET devices or circuits incorporating an improved substrate temperature sensing element are obtained by forming a PN junction directly on a thin (gate) dielectric region. The temperature sense junction is desirably formed in a poly layer. By mounting it directly on thin (gate) dielectric its thermal response to temperature changes in the substrate is improved while still being electrically isolated from the substrate. It is desirable to provide over-voltage protection elements coupled to the junction to avoid rupture of the underlying thin dielectric. Because the sense diode and all the over-voltage protection devices may be made of poly with junctions perpendicular to the substrate, the structure is particularly compact and simple to fabricate.

Abstract: MOSFET devices or circuits incorporating an improved substrate temperature sensing element are obtained by forming a PN junction directly on a thin (gate) dielectric region. The temperature sense junction is desirably formed in a poly layer. By mounting it directly on thin (gate) dielectric its thermal response to temperature changes in the substrate is improved while still being electrically isolated from the substrate. It is desirable to provide over-voltage protection elements coupled to the junction to avoid rupture of the underlying thin dielectric. Because the sense diode and all the over-voltage protection devices may be made of poly with junctions perpendicular to the substrate, the structure is particularly compact and simple to fabricate.

Abstract: A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is copupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

Abstract: A vertical field effect transistor having a first low resistivity region which determines breakdown voltage and a second low resistively region which is formed underneath a portion of a source is provided. The second low resistivity region lowers the gain of a parasitic bipolar transistor, and lowers resistance of a base region under the source of the field effect transistor, improving the commutating safe operating area of the vertical field effect transistor.