Abstract: A high speed memory interface for a processor-based computing system provides a bridge component (made up of a controller and a data path), one or more data multiplexer/buffers, and a plurality of RAS/CAS generators. The high speed memory interface allows for the expansion of the memory subsystem without additional loading on the processor/system bus and without a reduction in memory transaction performance. The interface includes a single controller for receiving memory transaction commands from the processor/system bus, and a plurality of RAS/CAS generators, for generating RAS/CAS signals in response to memory transaction commands forwarded by the controller. Each RAS/CAS generator is coupled to one or more memory banks. A data multiplexer/buffer is coupled to one or more of the memory banks, and provides an interface between the memory bank(s) and the data path.

Abstract: A system for detecting hazardous conditions during operation of a vehicle. In one embodiment, the system includes a plurality of sensors that monitor a plurality of conditions and transmit condition signals each representing a measure of a condition. A plurality of rate determination circuits is coupled to the sensors and continually receives the condition signals, wherein each rate determination circuit calculates rates of change for the condition, including a baseline rate of change, and outputs a potential hazard value representing a deviation of a rate of change from the baseline rate that exceeds a predetermined threshold value. An evaluation circuit receives the potential hazard value, calculates a new potential hazard value using the potential hazard value and a rate of change for at least one associated condition and determines whether an actual hazard exists by comparing the new potential hazard value with a stored value that corresponds to the condition.

Abstract: In one embodiment of the invention, an apparatus includes address and data ports to receive an interrupt request signal in the form of address signals and data signals. The apparatus also includes decode logic to receive at least some of the address signals and data signals and provide a decoded signal at one of several decode output lines of the decode logic. A redirection table includes a send pending bit that is set responsive to the decode signal. In another embodiment, an apparatus includes dedicated interrupt ports to receive an interrupt request signal. The apparatus also includes address and data ports capable of receiving an interrupt request signal in the form of address signals and data signals, and decode logic to provide a decode signal at one of several decode output lines in response to reception of the interrupt request signal in the form of address signals and data signals.

Abstract: A method and apparatus for ordering data transfers includes an identifier of a critical portion of data being received from a requesting agent along with a request for data. Writeback data corresponding to the requested data is then transferred to the bus as a plurality of portions and ordered to ensure that a first portion which includes the critical portion of the data is transferred to the bus first.

Abstract: A method and apparatus for transferring data between bus agents in a computer system including a bus operating at a bus clock rate. The method includes the step of receiving a transaction request from a requesting agent including an indication of a plurality of data widths the requesting agent processes. In response to the transaction request, a data transmission is configured in accordance with a data width that both the requesting agent and a responding agent process. The data transmission is performed asynchronously with respect to the bus clock if the data width is one of a first plurality of data widths, otherwise, the data transmission is performed synchronously with respect to the bus clock.

Abstract: In a method and apparatus for changing data transfer widths in a computer system, a first agent on a bus provides a first indication to a second agent on the bus identifying one or more data transfer widths supported by the first agent. The second agent then provides a second indication to the first agent identifying one or more data transfer widths supported by the second agent. A data transfer width is then determined based on the first indication and the second indication. According to an embodiment of the present invention, a third agent involved in a transaction is also able to provide a third indication to the first and/or second agents identifying one or more data transfer widths supported by the third agent. The data transfer width(s) is then determined based on the first, second, and third indications.

Abstract: Prior art methods of maintaining coherency among multiple TLBs in a multiprocessor system were time-consuming. One microprocessor halted all other microprocessors in the system, and sent an interrupt to each of the halted microprocessors. Rather than invoking an interrupt handler, the TLB shootdown operation of the present invention provides for a TLB flush transaction communicated between multiple processors on a host bus. One microprocessor issues a TLB flush request on the host bus. The TLB flush request includes a page number. The microprocessors receiving the request invalidate the TLB entry corresponding to the page number.

Abstract: A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlock-free operation. I/O to memory transactions and processor to memory transactions are placed in a memory request queue in the order in which such transactions appear on the processor bus; I/O to memory transactions are placed in an inbound request queue in the order such transactions appear on the I/O bus; and processor to I/O transactions and completions corresponding to split-transaction I/O to memory read transactions are placed in an outbound request queue in the order in which the split-transaction I/O to memory read transactions and the processor to I/O transactions appear on the processor bus.

Abstract: A computer memory subsystem and associated method are disclosed in which memory transaction latency and bandwidth in the memory subsystem are improved through the opportunistic transfer of write data from a data path to a memory buffer coupled to a targeted memory bank during an access latency period within a non-memory write operation, such as, e.g., a read or refresh operation. The opportunistic write data transfer operation utilizes otherwise unused memory data bus cycles within a read or refresh operation for performance of the write data transfer, without adding clock cycles to the read or refresh operation. Because the write data is transferred to the memory buffer coupled to the memory bank during the latency period of the memory operation preceding the write operation, the total turnaround time for, e.g., performing a read operation followed by a write operation is reduced.

Abstract: A method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller includes a memory controller having a data controller unit and a data path unit. Signals are passed between the data controller unit and the data path unit, thereby providing an interface between the two units. The data controller receives control signals from the bus and provides commands to the data path unit in response to these control signals. The commands provided to the data path unit enable the data path unit to transfer data to and from the bus and memory device.

Abstract: A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perform snoops in response to transaction requests providing snoop results and modified data within one transaction. Additionally, the system supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

Abstract: A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.

Abstract: A method and apparatus for tracking transactions in a pipelined bus includes a bus state tracking queue and control logic. The bus state tracking queue maintains a record of bus transaction information for each of a plurality of transactions pending on the bus. The control logic, coupled to the bus state tracking queue, updates the status of the plurality of transactions in the bus state tracking queue as the transactions progress through the pipeline.

Abstract: A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.

Abstract: A clocking scheme for transferring data between electronic devices. The clocking scheme includes sending a data request signal from a first device to a second device during a first system clocking period. The second device then sends the requested data and a corresponding data validation signal to the first device. The data validation signal latches the data into the second device. The data is latched by the validation signal in a time period that is typically shorter than the clocking period of the system clock.

Abstract: An asynchronous computer bus and method to maintain consistency of data contained in a cache and a memory which are each coupled to the bus. The bus comprises a cache hit indication means, a write access indication means, and a modified data indication means. A means is provided for invalidating a first portion of the cache, the invalidation means being operative upon activation of the cache hit indication means. Further, the bus comprises a modified data indication means and the write access indication means. A write-back means is provided for writing back the first portion of the cache data to the memory, the write back means being operative upon the first portion of the cache being invalidated by the invalidation means. Lastly, the bus comprises a shared data indication means which is operative on the cache hit indication means and upon failure of activation of the write access determination means.

Abstract: An asynchronous computer bus providing transfers of data on consecutive processor clock cycles. The bus comprises consecutive data transfer commence indication means, starting address transmission means, consecutive data transfer indication means, and data transmission means. The invention provides for the "burst" capabilities of modern processors wherein entire blocks of data are transmitted within a single request.