Abstract: A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number of ways. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. For example, in response to a processor core indicating that it is entering a period of reduced activity, the cache controller can reduce the number of ways available in each set of the cache.

Abstract: As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache.

Abstract: Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage threshold, and an interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold. Some embodiments of a method include providing a first test pattern to one or more power supply monitors associated with one or more circuit blocks in the processing device and capturing a first result generated by the power supply monitor(s) based on the first test pattern. The first result indicates whether a voltage provided to the circuit block(s) is below a voltage threshold.

Abstract: An integrated circuit device includes a first signal line for distributing a first signal. The first signal line includes a plurality of branch lines, and a leaf node is defined at an end of each branch line. First logic is coupled to the leaf nodes and operable to generate a first status signal indicative of a collective first logic state of the leaf nodes of the signal line corresponding to the first signal.

Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.

Abstract: Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.

Abstract: A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of <1 ms/DC sweep at <2 mV or <1 nA resolution accuracy of variations in voltage or current of the device under test. Salient features of proposed circuit architecture include a programmable ramp voltage generator that stimulates the device under test, a dual input 9-11 bit cyclic ADC that captures input and output DC voltage/current signals to/from the device under test, a 2 Kb latch bank that captures 9-11 bit streams for each measurement point in a DC sweep of programmable granularity and a clocking and control scheme that enables continuous measurement and stream out of digital data blocks from which the analog characteristics of the devices under test are reconstructed post measurement.

Abstract: A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.

Abstract: Various circuit board voltage regulators and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating at least one inductor in a circuit board and coupling a semiconductor chip to the circuit board. The at least one inductor is electrically coupled to the semiconductor chip. Regulator logic is electrically coupled to the at least one inductor, the regulator logic and the at least one inductor are operable to deliver a regulated voltage to the semiconductor chip.

Abstract: A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively.

Abstract: An integrated circuit (IC) is disclosed. The IC includes a first global voltage node and a second global voltage node. The IC further includes two or more power domains each coupled to the first global voltage node. Each of the two or more power domains includes a functional unit and a local voltage node coupled to the functional unit. Each of the plurality of power domains further includes a power-gating transistor coupled between the local voltage node and the second global voltage node, and an ESD (electrostatic discharge) circuit configured to detect an occurrence of an ESD event and further configured to cause activation of the transistor responsive to detecting the ESD event.

Abstract: Circuits for measuring and characterizing random variations in device characteristics of integrated circuit devices.

Abstract: Circuits and methods for measuring and characterizing random variations in device characteristics of semiconductor integrated circuit devices, which enable circuit designers to accurately measure and characterize random variations in device characteristics (such as transistor threshold voltage) between neighboring devices resulting from random sources such as dopant fluctuations and line edge roughness, for purposes of integrated circuit design and analysis. In one aspect, a method for characterizing random variations in device mismatch (e.g., threshold voltage mismatch) between a pair of device (e.g., transistors) is performed by obtaining subthreshold DC voltage characteristic data for the device pair, and then determining a distribution in voltage threshold mismatch for the device pair directly from the corresponding subthreshold DC voltage characteristic data.

Abstract: A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device.

Abstract: Power supply variations and jitter are measured by monitoring the performance of a ring oscillator on a cycle-by-cycle basis. Performance is measured by counting the number of stages of the ring oscillator that are traversed during the clock cycle and mapping the number of stages traversed to a particular voltage level. Counters are used to count the number of ring oscillator revolutions and latches are used to latch the state of the ring oscillator at the end of the cycle. Based on the counters and latches, a monitor output is generated that may also incorporate an adjustment for a reset delay associated with initializing the ring oscillator and counters to a known state.

Abstract: An integrated circuit (IC) is disclosed. The IC includes a first global voltage node and a second global voltage node. The IC further includes two or more power domains each coupled to the first global voltage node. Each of the two or more power domains includes a functional unit and a local voltage node coupled to the functional unit. Each of the plurality of power domains further includes a power-gating transistor coupled between the local voltage node and the second global voltage node, and an ESD (electrostatic discharge) circuit configured to detect an occurrence of an ESD event and further configured to cause activation of the transistor responsive to detecting the ESD event.

Abstract: A Circuit architecture and a method for rapid and accurate statistical characterization of the variations in the electrical characteristics of CMOS process structures, MOS devices and Circuit parameters is provided. The proposed circuit architecture and method enables a statistical characterization throughput of <1 ms/DC sweep at <2 mV or <1 nA resolution accuracy of variations in voltage or current of the device under test. Salient features of proposed circuit architecture include a programmable ramp voltage generator that stimulates the device under test, a dual input 9-11 bit cyclic ADC that captures input and output DC voltage/current signals to/from the device under test, a 2 Kb latch bank that captures 9-11 bit streams for each measurement point in a DC sweep of programmable granularity and a clocking and control scheme that enables continuous measurement and stream out of digital data blocks from which the analog characteristics of the devices under test are reconstructed post measurement.

Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

Abstract: A method, apparatus, computer chip, circuit board, computer and system are provided in which data is stored in a low-voltage, maskable memory. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus. The method includes storing a data value in a memory cell in a storage device if a first access parameter associated with the memory cell matches a first pre-determined value and if a second access parameter associated with the memory cell matches a second pre-determined value. The method also includes maintaining a data value in the memory cell in the storage device if the first access parameter differs from the first pre-determined value. The apparatus includes a first and second pair of access parameter ports operatively coupled together and associated with a first and second access parameter respectively.

Abstract: A power gate includes a series of electrical contacts along at least a portion of an integrated circuit and a series of power gate transistors electrically coupled to the electrical contacts on the integrated circuit to form a power gate boundary, e.g., at the integrated circuit periphery. The electrical contacts along at least a portion of a running length of the power gate boundary define a substantially non-linear profile. The non-linear profile provides increased contact density which improves current balancing across the electrical contacts and current throughput through the power gate. The non-linear profile is a sinusoidal or zigzag pattern with intermediate offset bump contacts. The contact profiles along the power gate boundary can include both linear and non-linear profiles.