Abstract: Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

Abstract: The present invention provides an improved SRAM cell. Specifically, the present invention provides an SRAM cell having one or more sets of stacked transistors for isolating the cell during a read operation. Depending on the embodiment, the SRAM cell of the present invention can have eight or ten transistors. Regardless, the SRAM cell of the present invention typically includes separate/decoupled write word and read word lines, a pair of cross-coupled inverters, and a complimentary pair of pass transistors that are coupled to the write word line. Each set of stacked transistors implemented within the SRAM cell has a transistor that is coupled to a bit line as well as the read word line.

Abstract: A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit.

Abstract: A device that includes an electronic device referred to as an integrated circuit interposer is disclosed. The integrated circuit includes a voltage regulator module. The interposer is attached to an electronic device, such as another integrated circuit, and facilitates control and distribution of power to the electronic device. The integrated circuit interposer can also conduct signaling between the attached electronic device and another electronic device. The voltage regulator module at the integrated circuit interposer can be configured to provide a voltage reference signal to the attached electronic device. Generation of the voltage reference signal by the integrated circuit interposer can be enabled or disabled and the value of the voltage reference signal can be adjusted, depending on operating requirements of the electronic device.

Abstract: A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.

Abstract: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch.

Abstract: Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught.

Abstract: A circuit incorporating a current starved ring oscillator is coupled to a power gate switch in an integrated circuit. The circuit incorporating the current starved ring oscillator amplifies a voltage difference between a virtual ground associated with the power gate switch and ground, and converts the difference to a frequency. Digital logic monitors the output of the ring oscillator using a counter and a reference clock. Control circuitry controls operation of the integrated circuit in dependence on the monitored conditions associated with the power gate switch. A method monitors a virtual ground voltage across a power gate switch in an integrated circuit; and controls operation of the integrated circuit in dependence on the monitored virtual ground voltage.

Abstract: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch.

Abstract: A method for executing multiple computational primitives is provided in accordance with exemplary embodiments. A first computational unit and at least a second computational unit cooperate to execute multiple computational primitives. The first computational unit independently computes other computational primitives. By virtue of arbitration for shared source operand buses or shared result buses, availability of the first and second computational units needed to execute cooperatively the multiple computational primitives is assured by a process of reservation as used for a computational primitive executed on a dedicated computational unit.

Abstract: Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.

Abstract: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.

Abstract: A method, system and computer program product for modeling and simulating a powergated hierarchical element of an integrated circuit is disclosed. In modeling a powergated macro, the invention does not model all logic gates or elements as powergated, instead, the invention only models latches as connected to an integrated switch to be powergated. In addition, a fence circuit attached to the powergated macro is modeled as including an extra control signal to force a powergated state of the powergated macro into the fence circuit.

Abstract: A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.

Abstract: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.

Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

Abstract: A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.

Abstract: An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers.

Abstract: Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.