Abstract: Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated.

Abstract: An interactive health monitoring system and corresponding method for dynamic monitoring of a physiological condition of a user may include collecting, by a monitoring device, measurements representing physiological signals of the body, transmitting the measurements from the monitoring device to a local device, and receiving, at a remote server, the measurements and additional data from the local device. The remote server may include a processing module, a review portal and a clinician portal, such that the remote server may be arranged to automatically classify the measurements representing physiological signals of the body, verify the classifications, and provide the verified measurements at a clinician portal. One or more of the monitoring device, the local device, the processing module, the reviewer portal and the clinician portal being configured to initiate a challenge and response request at the local device in response to predefined criteria.

Abstract: Methods, systems, and computer program products are described for generating synthesizable netlists from register transfer level (RTL) designs to aid with semiconductor device design. These netlists provide RTL design information corresponding to a portion of a semiconductor device. A configuration tracer generates behavior information associated with the RTL design. A register compiler compiles a set of semiconductor devices based on one or more technologies and power, performance, and area (PPA) information related to the semiconductor device. Semiconductor devices generated by the register compiler that meet predefined power, performance, and area conditions are identified. Structural information for aligning the input/output ports of the semiconductor device is generated.

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: Disclosed are compositions comprising a YAP1/WWRT1 inhibiting agent and a glutaminase inhibiting agent and methods of their use. Disclosed herein are therapeutic particles comprising a biocompatible polymer, a YAP1/WWRT1 inhibiting agent, and a glutaminase inhibiting agent. In one aspect, disclosed herein are methods of treating a pulmonary disease in a subject in need of such treatment comprising administering the therapeutic particle to the subject.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: Disclosed are pathogenic mechanisms in pulmonary hypertension and molecular inhibitors of the same. Particularly, GSTP1 (glutathione S-transferase P1) have been demonstrated as having a role in regulating the endothelial ISCU function in pulmonary hypertension. Accordingly, methods for treating pulmonary hypertension in a subject in need thereof comprising administering a therapeutically effective amount of a pharmaceutical composition that inhibits glutathione S-transferase P (GSTP1) and/or increasing ISCU expression are disclosed. The GSTP1 inhibitor can comprise a piperlongumine analog, such as BRD-K34222889, or a derivative thereof.

Abstract: Provided herein are methods of treating a disease or condition in a patient, such as pulmonary hypertension, having one or more Gs at SNV rs73184087, comprising editing one or both G's at rs73184087 in the patient. Provided herein also are methods of treating a disease or condition in a patient, having one or more As, Ts or Gs at SNV rs73184087, comprising substituting one or both As, Ts or Gs at rs73184087 in the patient with a G. Also provided herein is an iPSC cell or a cell differentiated from the iPSC cell, homozygous for G at SNV rs73184087, having use in screening drugs for their ability to treat a hypoxia-related or ischemia-related disease or condition in a patient, such as pulmonary hypertension.

Abstract: Described herein are systems, methods, and software to handle requests to an application file shared by a plurality of applications on a computing system. In one implementation, a method of handling request for an application file shared by a plurality of applications on a computing system includes identifying a request for the application file on the computing system, wherein each application in the plurality of applications is associated with an individualized version of the application file, and wherein the plurality of applications is stored on separate application storage volumes attached to the computing system. The method further provides identifying an application associated with the request, and identifying an application storage volume in the application storage volumes that stores the application. Once identified, the method also includes retrieving the application file from the identified storage volume to support the request.

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: Provided herein are methods of treating a coronavirus infection in a patient, comprising administering an agent to the patient in an amount effective to increase cellular lysosomal pH in cells of the patient. As provided herein, the agent is one or more of an agent for reducing expression or activity of nuclear receptor coactivator 7 (NCOA7) in the patient, an RNAi agent or antisense reagent for knocking down expression of a v-rel avian reticuloendotheliosis viral oncogene homolog A (RelA/p65) transcript, or a janus kinase (JAK) inhibitor, thereby increasing cellular lysosomal pH in cells of the patient.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.

Abstract: Disclosed herein are compositions and methods for treating pulmonary hypertension whereby a SCUBE1 polynucleotide or polypeptide is administered. Also disclosed herein are methods for diagnosing and/or prognosing pulmonary arterial hypertension or pulmonary hypertension with high pulmonary vascular resistance that include detecting an amount of a SCUBE1 polynucleotide or polypeptide.

Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.