Patents by Inventor Stephen Yu

Stephen Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135078
    Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.
    Type: Application
    Filed: January 4, 2024
    Publication date: April 25, 2024
    Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
  • Publication number: 20240126864
    Abstract: Examples of determining electronic component authenticity via electronic signal signature measurement are discussed. Reference pin identifiers corresponding to pins of a known authentic electronic component are determined. Measurement values corresponding to characteristics of pins of an electronic component are obtained, and pin identifiers based on the measurement values are generated. Accordingly, an indication that the electronic component is authentic can be provided based at least in part on a comparison of the pin identifiers and the reference pin identifiers.
    Type: Application
    Filed: August 21, 2023
    Publication date: April 18, 2024
    Inventors: Yunghsiao CHUNG, Feng YU, Stephen Edward SADDOW
  • Patent number: 11960920
    Abstract: A data management system comprises: a storage appliance configured to store a snapshot of a virtual machine; and one or more processors in communication with the storage appliance. The one or more processors are configured to perform operations including: identifying a plurality of shards of the virtual machine; requesting a snapshot of each of the plurality of shards; receiving the shards asynchronously; ordering the received snapshot shards sequentially into a results queue; and storing a single snapshot of the virtual machine based on the ordered snapshot shards. Operations may further include maintaining a flow control queue that limits the number of snapshot shards requested.
    Type: Grant
    Filed: May 11, 2023
    Date of Patent: April 16, 2024
    Assignee: Rubrik, Inc.
    Inventors: Christopher Denny, Li Ding, Linglin Yu, Stephen Chu, Ying Wu
  • Patent number: 11952420
    Abstract: Provided herein are antibodies, or antigen-binding portions thereof, that specifically bind and inhibit TREM-1 signaling, wherein the antibodies do not bind to one or more Fc?Rs and do not induce the myeloid cells to produce inflammatory cytokines. Also provided are uses of such antibodies, or antigen-binding portions thereof, in therapeutic applications, such as treatment of autoimmune diseases.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: April 9, 2024
    Assignee: BRISTOL-MYERS SQUIBB COMPANY
    Inventors: Achal Pashine, Michael L Gosselin, Aaron P. Yamniuk, Derek A. Holmes, Guodong Chen, Priyanka Apurva Madia, Richard Yu-Cheng Huang, Stephen Michael Carl
  • Patent number: 11945772
    Abstract: A method including the step contacting an olefin, an alcohol, a metallosilicate catalyst and a solvent, wherein the solvent comprises structure (I): wherein R1 and R2 are each selected from the group consisting of an aryl group and an alkyl group with the proviso that at least one of R1 and R2 is an aryl group, further wherein n is 1-3.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 2, 2024
    Assignee: Dow Global Technologies LLC
    Inventors: Wen-Sheng Lee, Mingzhe Yu, Jing L. Houser, Sung-Yu Ku, Wanglin Yu, Stephen W. King, Paulami Majumdar, Le Wang
  • Patent number: 11948379
    Abstract: A system including at least one processor; and at least one memory having stored thereon computer program code that, when executed by the at least one processor, controls the at least one processor to: receive an email addressed to a user; separate the email into a plurality of email components; analyze, using respective machine-learning techniques, each of the plurality of email components; feed the analysis of each of the plurality of email components into a stacked ensemble analyzer; and based on an output of the stacked ensemble analyzer, determine whether the email is malicious.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: April 2, 2024
    Assignee: CAPITAL ONE SERVICES, LLC
    Inventors: Christopher Bayan Bruss, Stephen Fletcher, Lei Yu, Jakob Kressel
  • Publication number: 20240082158
    Abstract: Disclosed are compositions comprising a YAP1/WWRT1 inhibiting agent and a glutaminase inhibiting agent and methods of their use. Disclosed herein are therapeutic particles comprising a biocompatible polymer, a YAP1/WWRT1 inhibiting agent, and a glutaminase inhibiting agent. In one aspect, disclosed herein are methods of treating a pulmonary disease in a subject in need of such treatment comprising administering the therapeutic particle to the subject.
    Type: Application
    Filed: July 11, 2023
    Publication date: March 14, 2024
    Inventors: Abhinav Prakash ACHARYA, Stephen Yu-Wah CHAN, Steven R. LITTLE
  • Patent number: 11919962
    Abstract: Provided herein are antibodies that bind to the alpha subunit of an IL-7 receptor (IL-7R?). Also provided are uses of these antibodies in therapeutic applications, such as treatment of inflammatory diseases. Further provided are cells that produce the antibodies, polynucleotides encoding the heavy and/or light chain regions of the antibodies, and vectors comprising the polynucleotides.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: March 5, 2024
    Assignee: Bristol Myers-Squibb Company
    Inventors: Aaron Paul Yamniuk, Scott Ronald Brodeur, Ekaterina Deyanova, Richard Yu-Cheng Huang, Yun Wang, Alfred Robert Langish, Guodong Chen, Stephen Michael Carl, Hong Shen, Achal Mukundrao Pashine, Lin Hui Su
  • Patent number: 11919954
    Abstract: Provided herein are antibodies, or antigen-binding portions thereof, that specifically bind and inhibit TREM-1 signaling, wherein the antibodies do not bind to one or more Fc?Rs and do not induce the myeloid cells to produce inflammatory cytokines. Also provided are uses of such antibodies, or antigen-binding portions thereof, in therapeutic applications, such as treatment of autoimmune diseases.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: March 5, 2024
    Assignee: BRISTOL-MYERS SQUIBB COMPANY
    Inventors: Achal Pashine, Michael L. Gosselin, Aaron P. Yamniuk, Derek A. Holmes, Guodong Chen, Priyanka Apurva Madia, Richard Yu-Cheng Huang, Stephen Michael Carl
  • Patent number: 11914562
    Abstract: A method and system for managing searches of a data set that is partitioned based on a plurality of events. A structure of a search query may be analyzed to determine if logical computational actions performed on the data set is reducible. Data in each partition is analyzed to determine if at least a portion of the data in the partition is reducible. In response to a subsequent or reoccurring search request, intermediate summaries of reducible data and reducible search computations may be aggregated for each partition. Next, a search result may be generated based on at least one of the aggregated intermediate summaries, the aggregated reducible search computations, and a query of adhoc non-reducible data arranged in at least one of the plurality of partitions for the data set.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: February 27, 2024
    Assignee: SPLUNK INC.
    Inventors: Ledion Bitincka, Stephen Phillip Sorkin, Steve Yu Zhang
  • Patent number: 11900037
    Abstract: Systems, methods, and computer programs products are described for optimizing circuit synthesis for implementation on an integrated circuit. A register transfer level code description of logic behavior of a circuit. The register transfer level code description is converted into structurally defined circuit designs for multiple types of components and feature size technologies. A floor plan of each structurally defined circuit design is generated. A physically simulated circuit is created for each floor plan. A range of operating conditions is swept over to analyze power, performance, and area of each physically simulated circuit.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu, Yi-Lin Chuang, Chih-Sheng Hou
  • Patent number: 11900035
    Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu
  • Publication number: 20240037302
    Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 1, 2024
    Inventors: Chih-yuan Stephen YU, Boh-Yi HUANG, Chao-Chun LO, Xiang GUO
  • Publication number: 20230414590
    Abstract: Disclosed are pathogenic mechanisms in pulmonary hypertension and molecular inhibitors of the same. Particularly, GSTP1 (glutathione S-transferase P1) have been demonstrated as having a role in regulating the endothelial ISCU function in pulmonary hypertension. Accordingly, methods for treating pulmonary hypertension in a subject in need thereof comprising administering a therapeutically effective amount of a pharmaceutical composition that inhibits glutathione S-transferase P (GSTP1) and/or increasing ISCU expression are disclosed. The GSTP1 inhibitor can comprise a piperlongumine analog, such as BRD-K34222889, or a derivative thereof.
    Type: Application
    Filed: November 9, 2021
    Publication date: December 28, 2023
    Inventors: Stephen Yu-Wah CHAN, Seungchan KIM
  • Publication number: 20230340463
    Abstract: Provided herein are methods of treating a disease or condition in a patient, such as pulmonary hypertension, having one or more Gs at SNV rs73184087, comprising editing one or both G's at rs73184087 in the patient. Provided herein also are methods of treating a disease or condition in a patient, having one or more As, Ts or Gs at SNV rs73184087, comprising substituting one or both As, Ts or Gs at rs73184087 in the patient with a G. Also provided herein is an iPSC cell or a cell differentiated from the iPSC cell, homozygous for G at SNV rs73184087, having use in screening drugs for their ability to treat a hypoxia-related or ischemia-related disease or condition in a patient, such as pulmonary hypertension.
    Type: Application
    Filed: April 25, 2023
    Publication date: October 26, 2023
    Inventor: Stephen Yu-Wah Chan
  • Patent number: 11792278
    Abstract: Described herein are systems, methods, and software to handle requests to an application file shared by a plurality of applications on a computing system. In one implementation, a method of handling request for an application file shared by a plurality of applications on a computing system includes identifying a request for the application file on the computing system, wherein each application in the plurality of applications is associated with an individualized version of the application file, and wherein the plurality of applications is stored on separate application storage volumes attached to the computing system. The method further provides identifying an application associated with the request, and identifying an application storage volume in the application storage volumes that stores the application. Once identified, the method also includes retrieving the application file from the identified storage volume to support the request.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 17, 2023
    Assignee: VMware, Inc.
    Inventors: Zhikai Chen, Zhibin He, Tracy Yan Chi, Stephen Yu
  • Patent number: 11783104
    Abstract: A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: October 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-yuan Stephen Yu, Boh-Yi Huang, Chao-Chun Lo, Xiang Guo
  • Patent number: 11773391
    Abstract: Provided herein are methods of treating a coronavirus infection in a patient, comprising administering an agent to the patient in an amount effective to increase cellular lysosomal pH in cells of the patient. As provided herein, the agent is one or more of an agent for reducing expression or activity of nuclear receptor coactivator 7 (NCOA7) in the patient, an RNAi agent or antisense reagent for knocking down expression of a v-rel avian reticuloendotheliosis viral oncogene homolog A (RelA/p65) transcript, or a janus kinase (JAK) inhibitor, thereby increasing cellular lysosomal pH in cells of the patient.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 3, 2023
    Assignee: University of Pittsburgh—Of the Commonwealth System of Higher Education
    Inventors: Stephen Yu-Wah Chan, LLoyd David Harvey
  • Publication number: 20230205958
    Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).
    Type: Application
    Filed: March 1, 2023
    Publication date: June 29, 2023
    Inventors: Chao-Chun Lo, Boh-Yi Huang, Chih-yuan Stephen Yu
  • Patent number: D1018975
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 19, 2024
    Assignee: Dyson Technology Limited
    Inventors: Emily Mary Menzies, James Robert Alexander Fisher, Wee Guan Tan, Nicklaus Yu, David Oliver Williams, Phey Hong Soh, Stephen Benjamin Courtney