Abstract: Systems and method for making flexible and rigid interposers for use in the semiconductor industry. Electroless plating processes are used to minimize the costs associated with the production of flexible interposers while increasing the yield and life-cycle of the interposers. Electrical contact regions are more easily isolated using the electroless processes and risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. The rigid interposers include a pin projecting from a probe pad affixed to a substrate. The pin is aligned with conductive vias in the underlying wafer. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches of as little as 25 ?m.

Abstract: A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

Abstract: Hybrid molds for molding a multiplicity of solder balls for use in a molten solder screening process and methods for preparing such molds are disclosed. A method for forming the multiplicity of cavities in a pyramidal shape by anisotropically etching a crystalline silicon substrate along a specific crystallographic plane is utilized to form a crystalline silicon face plate used in the present invention hybrid mold. In a preferred embodiment, a silicon face plate is bonded to a borosilicate glass backing plate by adhesive means in a method that ensures coplanarity is achieved between the top surfaces of the silicon face plate and the glass backing plate. In an alternate embodiment, an additional glass frame is used for bonding a silicon face plate to a glass backing plate, again with ensured coplanarity between the top surfaces of the silicon face plate and the glass frame. In a second alternate embodiment, a silicon face plate is encased in an extender material which may be borosilicate glass or a polymer.

Abstract: A structure that includes a substrate, typically a semiconductor chip such as a VCSEL or photodetector chip, and a guide for aligning a signal conveying device, typically an optical fiber, to a transducer such as an optoelectronic device on the semiconductor chip. The guide is formed, in a preferred embodiment, by lithographically exposing and developing a thick layer of photoresist. The structure is assembled by placing and securing the signal conveying device into a cavity-like region of the guide.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: Hybrid molds for molding a multiplicity of solder balls for use in a molten solder screening process and methods for preparing such molds are disclosed. A method for forming the multiplicity of cavities in a pyramidal shape by anisotropically etching a crystalline silicon substrate along a specific crystallographic plane is utilized to form a crystalline silicon face plate used in the present invention hybrid mold. In a preferred embodiment, a silicon face plate is bonded to a borosilicate glass backing plate by adhesive means in a method that ensures coplanarity is achieved between the top surfaces of the silicon face plate and the glass backing plate. In an alternate embodiment, an additional glass frame is used for bonding a silicon face plate to a glass backing plate, again with ensured coplanarity between the top surfaces of the silicon face plate and the glass frame. In a second alternate embodiment, a silicon face plate is encased in an extender material which may be borosilicate glass or a polymer.

Abstract: A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: A method for forming three-dimensional circuitization in a substrate is provided for forming conductive traces and via contacts. In the method, a substrate formed of a substantially insulating material is first provided, grooves and apertures in a top surface of and through the substrate are then formed, followed by filling the grooves and apertures with an electrically conductive material such as a solder. The method can be carried out at a low cost to produce high quality circuit substrates by utilizing an injection molded solder technique or a molten solder screening technique to fill the grooves and the apertures. The grooves and the apertures in the substrate may be formed by a variety of techniques such as chemical etching, physical machining and hot stamping.

Abstract: Hybrid molds for molding a multiplicity of solder balls for use in a molten solder screening process and methods for preparing such molds are disclosed. A method for forming the multiplicity of cavities in a pyramidal shape by anisotropically etching a crystalline silicon substrate along a specific crystallographic plane is utilized to form a crystalline silicon face plate used in the present invention hybrid mold. In a preferred embodiment, a silicon face plate is bonded to a borosilicate glass backing plate by adhesive means in a method that ensures coplanarity is achieved between the top surfaces of the silicon face plate and the glass backing plate. In an alternate embodiment, an additional glass frame is used for bonding a silicon face plate to a glass backing plate, again with ensured coplanarity between the top surfaces of the silicon face plate and the glass frame. In a second alternate embodiment, a silicon face plate is encased in an extender material which may be borosilicate glass or a polymer.

Abstract: A thermoelectric device with enhanced structured interfaces for improved cooling efficiency is provided. In one embodiment, the thermoelectric device includes a first thermoelement comprising a supetlattice of p-type thermoelectric material and a second thermoelement comprising superlattice of n-type thermoelectric material. The first and second thermoelements are electrically coupled to each other. The first thermoelement is proximate to, without necessarily being in physical contact with, a first array of electrically conducting tips at a discrete set of points. A planer surface of the second thermoelement is proximate to, without necessarily being in physical contact with, a second array of electrically conducting tips at a discrete set of points. The electrically conducting tips are coated with a material that has the same Seebeck coefficient as the material of the nearest layer of the superlattice to the tip.

Abstract: A novel optoelectronic packaging submount arrangement which incorporates a 90° C. electrical conductor turn, and more specifically methods of producing optoelectronic packaging submount arrangement incorporating 90° C. electrical conductor turns.

Abstract: A precise volume, precisely registerable carrier is provided for use with injection molding for producing integrated circuit bump contacts in the “flip chip” technology. A hemispherical cavity is produced by etching through and undercutting a registered opening into a transparent carrier. The hemispherical cavity has related specific volume and visible peripheral shape that permits simple optical quality control when the injection molding operation has filled the cavity and simple optical registration for fusing to the pads on the integrated circuit.

Abstract: A precise volume, precisely registerable carrier is provided for use with injection molding for producing integrated circuit bump contacts in the "flip chip" technology. A hemispherical cavity is produced by etching through and undercutting a registered opening into a transparent carrier. The hemispherical cavity has related specific volume and visible peripheral shape that permits simple optical quality control when the injection molding operation has filled the cavity and simple optical registration for fusing to the pads on the integrated circuit.