Patents by Inventor Steven Bartling
Steven Bartling has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230195984Abstract: A method for timing analysis includes receiving a physical design of an electric circuit, selecting a timing path within the electric circuit, and determining that the selected timing path includes a first logic cell implemented with a first type of transistor and a second logic cell implemented with a second type of transistor. The method further includes running a set of process corners with the first type of transistor at a given corner and the second type of transistor at a condition other than the given corner. The first type of transistor has a delay that is based on process correlation with the second type of transistor. The method also includes determining whether a timing requirement is met or not met for the selected timing path, and then reporting whether the timing requirement is met or not met.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Inventors: Ajoy MANDAL, Venkatraman RAMAKRISHNAN, Steven BARTLING
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Patent number: 11449341Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.Type: GrantFiled: September 9, 2019Date of Patent: September 20, 2022Assignee: Texas Instruments IncorporatedInventors: Marko Krüger, Steven Bartling, Markus Kösler
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Patent number: 10837845Abstract: Circuitry for determining the direction of incidence of an acoustic signal in an integrated circuit. An electronic circuit includes a packaged integrated circuit. The packaged integrated circuit includes a die. The die includes a plurality of acoustic transducers spaced apart on the die, and a measurement circuit. The plurality of acoustic transducers includes at least a first acoustic transducer and a second acoustic transducer. The measurement circuit is coupled to at least the first acoustic transducer and the second acoustic transducer. The measurement circuit is configured to determine for the first acoustic transducer, a first time at which the first acoustic transducer detects an acoustic signal propagating in the die; and determine for the second acoustic transducer, a second time at which the second acoustic transducer detects the acoustic signal propagating in the die.Type: GrantFiled: December 20, 2018Date of Patent: November 17, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ralf Peter Brederlow, Steven Bartling
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Publication number: 20200200618Abstract: Circuitry for determining the direction of incidence of an acoustic signal in an integrated circuit. An electronic circuit includes a packaged integrated circuit. The packaged integrated circuit includes a die. The die includes a plurality of acoustic transducers spaced apart on the die, and a measurement circuit. The plurality of acoustic transducers includes at least a first acoustic transducer and a second acoustic transducer. The measurement circuit is coupled to at least the first acoustic transducer and the second acoustic transducer. The measurement circuit is configured to determine for the first acoustic transducer, a first time at which the first acoustic transducer detects an acoustic signal propagating in the die; and determine for the second acoustic transducer, a second time at which the second acoustic transducer detects the acoustic signal propagating in the die.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: Ralf Peter BREDERLOW, Steven BARTLING
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Publication number: 20200073667Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.Type: ApplicationFiled: September 9, 2019Publication date: March 5, 2020Inventors: Marko Krüger, Steven Bartling, Markus Kösler
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Patent number: 10409607Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.Type: GrantFiled: June 15, 2015Date of Patent: September 10, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Marko Krüger, Steven Bartling, Markus Kösler
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Patent number: 9746868Abstract: A system comprising an ambient energy source, a power supply, and a power storage device. The ambient energy source is coupled to a first terminal end of an inductor. The power supply is also coupled to the first terminal end of the inductor. The power storage device is coupled to a second terminal end of the inductor. The ambient energy source provides power through the inductor in a first direction to the power storage device. The power storage device provides power through the inductor to the power supply in a second direction opposite the first direction.Type: GrantFiled: February 15, 2013Date of Patent: August 29, 2017Assignee: Texas Instruments IncorporatedInventors: Aatmesh Shrivastava, Yogesh Ramadass, Steven Bartling
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Patent number: 9270257Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.Type: GrantFiled: August 8, 2014Date of Patent: February 23, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna
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Publication number: 20150309801Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.Type: ApplicationFiled: June 15, 2015Publication date: October 29, 2015Inventors: Marko Krueger, Steven Bartling, Markus Koesler
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Patent number: 9160314Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.Type: GrantFiled: August 12, 2014Date of Patent: October 13, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna
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Patent number: 9099998Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.Type: GrantFiled: August 22, 2013Date of Patent: August 4, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna
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Patent number: 9086887Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.Type: GrantFiled: September 9, 2011Date of Patent: July 21, 2015Assignee: TEXAS INSTRUMENT INCORPORATEDInventors: Marko Krüger, Steven Bartling, Markus Kösler
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Patent number: 9088271Abstract: In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal (CKT) goes high, (CLKZ) goes low and retention control signal is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit (D2), the clock signals (CKT) and (CLKN), the retain control signals (RET) and the control signals SS (SS) and (SSN). The signals (CKT), (CLKZ), (RET), (SS) and (SSN) determine whether the output of the clocked inverter or the second data bit (D2) is latched in the dual-port latch. Control signal (RET) determines when data is stored in the dual-port latch during retention mode.Type: GrantFiled: September 24, 2013Date of Patent: July 21, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna
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Patent number: 9083328Abstract: In an embodiment of the invention, a flip-flop circuit contains a first inverter, a pass gate, master latch, a transfer gate and a slave latch. The clock signals and retention control signals determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals, the retain control signals, the slave control signals. The clock signals, the retain control signals, and the slave control signals determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. The retain control signals determine when data is stored in the slave latch during retention mode.Type: GrantFiled: August 12, 2014Date of Patent: July 14, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna
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Patent number: 9007111Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SS, RE and REN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.Type: GrantFiled: January 14, 2014Date of Patent: April 14, 2015Assignee: Texas Instruments IncorporatedInventors: Steven Bartling, Sudhanshu Khanna
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Publication number: 20150048872Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.Type: ApplicationFiled: August 8, 2014Publication date: February 19, 2015Applicant: Texas Instruments IncorporatedInventors: Steven Bartling, Sudhanshu Khanna
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Publication number: 20150042390Abstract: In an embodiment of the invention, a dual-port positive level sensitive data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and the control signals SS and SSN. The signals CKT, CLKZ, RET, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.Type: ApplicationFiled: September 24, 2013Publication date: February 12, 2015Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna
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Publication number: 20140347113Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.Type: ApplicationFiled: August 12, 2014Publication date: November 27, 2014Applicant: Texas Instruments IncorporatedInventors: Steven Bartling, Sudhanshu Khanna
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Publication number: 20140347114Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.Type: ApplicationFiled: August 12, 2014Publication date: November 27, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna
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Publication number: 20140328115Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.Type: ApplicationFiled: August 22, 2013Publication date: November 6, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Bartling, Sudhanshu Khanna