Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN RE, and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SS, RE and REN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLKN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN RE, and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. Clock signals CKT and CLKZ and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CKT, CLKZ, RET, RETN, SS, SSN and PREN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: A system comprising an ambient energy source, a power supply, and a power storage device. The ambient energy source is coupled to a first terminal end of an inductor. The power supply is also coupled to the first terminal end of the inductor. The power storage device is coupled to a second terminal end of the inductor. The ambient energy source provides power through the inductor in a first direction to the power storage device. The power storage device provides power through the inductor to the power supply in a second direction opposite the first direction.

Abstract: The invention relates to an electronic device for data processing, which includes an execution unit with a temporary register, a register file, a first feedback path from the data output of the execution unit to the register file, a second feedback path from the data output of the execution unit to the temporary register, a switch configured to connect the first feedback path and/or the second feedback path, and a logic stage coupled to control the switch. The control stage is configured to control the switch to connect the second feedback path if the data output of an execution unit is used as an operand in the subsequent operation of an execution unit.

Abstract: A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.

Abstract: A process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes applying a disturb voltage prior to a recall operation. Also, a process of testing an integrated circuit containing a programmable data storage component containing at least two ferroelectric capacitors coupled to complementary state nodes that includes adjusting a disturb voltage and determining if a screening data value and a read data value meet a criterion for determining a limiting disturb voltage.

Abstract: An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respect to the input delay signal. (B) A latch coupled with the delay unit to selectively keep the delay unit input signal at at least one predetermined signal level.

Abstract: A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing units of the co-processor, and also a bus slave circuit coupled to a system bus of the system, to selected ones of the memory blocks. The memory switch may be constructed as an array of multiplexers, controlled by control logic of the memory switch in response to the contents of a control register. The various processing units of the co-processor are each able to directly access one of the memory blocks, as controlled by the switch circuitry. Following processing of a block of data by one of the processing units, the memory switch associates the memory blocks with other functional units, thus moving data from one functional unit to another without requiring reading and rewriting of the data.

Abstract: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.

Abstract: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to said master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. The digital storage element operates in a functional mode or in a scan mode. While in the scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch. The first and second clock signals are non-overlapping and, as such, avoid the digital storage element from creating hold violations.